QuickLogic Corporation Aktie

Ladies and gentlemen, good afternoon. At this time, I would like to welcome everybody to QuickLogic Corporation's First Quarter Fiscal 2026 Earnings Results Conference Call. As a reminder, today's call is being recorded for replay purposes. I would now like to turn the conference over to Ms. Alison Ziegler of Darrow Associates.

Ms. Ziegler, you may proceed.

Thank you, Sherry, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer; and Elias Nader, Senior Vice President and Chief Financial Officer.

As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including, but not limited to, statements regarding our future profitability and cash flows, expectations regarding our future business and statements regarding the timing, milestones and payments related to our government contracts, statements regarding the expected magnitude of potential contracts and statements regarding expected adoption rates and/or orders by our customers.

Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risks that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis; our ability to adequately market the low-power competitive pricing and short time to market of our new products; intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters and other business interruptions that could disrupt supply or delivery of or demand for the company's products and changes in tax rates and exposure to additional tax liabilities.

For more detailed discussions of the risks, uncertainties and assumptions that could result in these differences, please refer to the risk factors discussed in QuickLogic's most recently filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information, which speak as of the respective dates of any new information or future events.

In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR web page that provides current and historical non-GAAP data.

Please note, QuickLogic uses its website, the company blog, corporate Twitter account, Facebook page and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR web page shortly after the conclusion of today's earnings call.

I'd now like to turn the call over to Brian. Go ahead, Brian.

Thank you, Alison. Good afternoon, everyone, and thank you all for joining our first quarter 2026 conference call.

Since our last conference call, we have made significant progress toward our goal of delivering 50% to 100% year-over-year revenue growth in 2026. With this, we continue to expect storefront and our new RadPro FPGA will contribute to our anticipated revenue growth and second half profitability.

As we announced in an April 9 press release, we introduced and demonstrated our new RADPro FPGA and development kit at the Hardened Electronics and Radiation Technology, or HEART Conference last month. HEART is a highly specialized conference where attendees must show proof of U.S. citizenship and their affiliation with a company or academia that is certified through the joint certification program.

RADPro is our trademark brand for radiation-hardened FPGAs. The test chip we demonstrated at the HEART Conference with our RADPro dev kit was internally funded and is independent of our U.S. government contract. These test chips were fabricated on GlobalFoundries' 12LP Process, which is the same process used by many DIBs for radiation-hardened ASICs. This means that in addition to successfully demonstrating our new discrete RADPro FPGA, we have also illustrated our capability to support requirements for eFPGA and radiation hardened ASICs and SoCs fabricated on the GlobalFoundries 12LP process.

Our demonstrations and meetings at HEART with leading DIBs went very well, and we have since shipped multiple RADPro dev kits. These shipments will provide a low six-figure contribution to our Q2 revenue. While we expect it will take until the end of 2026 for DIBs to fully evaluate our new RADPro FPGA, we have already signed an MOU with one DIB to accelerate the mutual evaluation of a potential RadPro chiplet application.

In addition to the progress we've made with our RADPro FPGA, in a March 17 press release, we announced our fourth contract targeting Intel 18A technology. While these initial contracts have been smaller, their total value is now nearly $2 million. And together, they are the framework for the larger contracts we expect to book later this year. The first two contracts were for Intel 18A test chips. We anticipate receiving our test chip allocation from the first contract later this quarter. We believe the data we gather from our evaluation of these test chips will enhance our ability to win new production contracts.

The third contract was for a 1 million LUT Feasibility Study, which led us to implement some notable architectural enhancements that we can leverage across all advanced fabrication nodes. With these architectural enhancements in place, we can address the lucrative markets that require very high-density eFPGA cores in ASIC designs and very high-density discrete FPGAs. This significantly expands our SRAM for eFPGA hard IP and discrete devices, including chiplets and a variety of storefront opportunities.

The fourth and most recent contract leverages the architectural enhancements that were developed during the 1 million LUT Feasibility Study. In support of this contract, we will deliver hard IP for a very large Intel 18A eFPGA core in support of our customers' ASIC design. The test chip for this ASIC design is targeted for tape-out during the second half of 2026.

We anticipate a fifth mid-6-figure contract from this customer during the second half of 2026 that further extends our work on very high-density architecture. While the timing of funding remains uncertain, our discussions with this DIB have expanded to include the potential of QuickLogic providing storefront services for a customer-designed ASIC that will include our eFPGA hard IP. We expect to learn more about the potential expansion to storefront services and the timing of this possible award in the coming months.

In addition to these DIB contracts, we are working closely with a large commercial customer contract based on Intel 18A valued at several million dollars. In our last conference call, I said that I expected this contract would be awarded in late Q2. However, the customer is evaluating an expansion in the size and function of the eFPGA core in their ASIC to provide greater programmable flexibility. While this is a beneficial trend for QuickLogic, we are now forecasting this contract to be awarded during Q3.

On December 8, we issued a press release announcing Idaho Scientific selected our eFPGA hard IP for forward-leaning hardware-based cryptographic solutions designed to address mobile IoT infrastructure and defense systems applications. We are continuing to support the integration of our hard IP into the tape-out that is anticipated next year. Idaho Scientific has a rich history in leveraging FPGA technology to deliver robust security systems that can adapt quickly to changing external threats without the vulnerabilities that are inherent in software-based solutions. By integrating our eFPGA hard IP into its secure system on a chip processors, Idaho Scientific can further enhance its cryptographic security and address new markets much more quickly with lower risks and lower costs. Since our last conference call, Idaho Scientific has been fully integrated with General Dynamics Mission Systems. We believe this integration may lead to new opportunities for QuickLogic.

Last year, we announced an eFPGA hard IP contract with a new defense industrial-based customer valued at $1.1 million that will be fabricated on the GF 12LP process. This application utilizes a large block of our eFPGA hard IP for critical functions, which is a trend we are seeing in designs targeting advanced fabrication nodes. With the cooperation of this DIB and its end customer, we have leveraged the large eFPGA core to win a new seven-figure contract that was finalized last week and will contribute to Q2 revenue. The delay of this award is why our Q1 revenue was below the midpoint of our guidance.

In the scope of this new contract, we will be provided with test chips that we will incorporate in an evaluation kit. The evaluation kit, which is currently scheduled for late 2026, will be compatible with common third-party development environments used by both DIBs and commercial customers. This enables these customers to accelerate system-level evaluations and designs that can use either a storefront version of the discrete FPGA or our eFPGA hard IP in an ASIC.

In parallel with these efforts, we're exploring the potential to leverage the FPGA from this contract as a storefront chiplet. We are already seeing interest from some of our partners on this concept. Due largely to the strategic initiatives we launched in 2025, we believe we are building meaningful traction in the chiplet markets. We are currently working on numerous proposals at various stages that include direct U.S. government, DIB and commercial applications. These proposals include opportunities targeting several fabrication processes, including GlobalFoundries 12LP and Intel 18A.

Last year, the commercial chiplet ecosystem was mired in debate regarding the communications and protocol layers. In response, we introduced the first phase of our digital proof-of-concept chiplet program as a strategy to move forward prior to customer commitments and with that, accelerate our storefront chiplet initiatives. Internally, we refer to this as POC.

With the support of our large strategic partners, we leveraged our existing eFPGA hard IP and readily available third-party IP to move this program forward rapidly and with minimal investment. We presented a paper on the POC at the Chiplet Summit in mid-February and gave a presentation with Intel Foundry at an event at the Government Microcircuit Applications and Critical Technology, or GOMACTech Conference in March. As a reminder, QuickLogic is a member of the Intel Foundry Accelerator Ecosystem Alliance Program, participating in the chiplet, IP and USMAG Alliances.

In our last conference call, I stated that the net takeaway from our presentation at the Chiplet Summit supports our optimism that chiplets will build traction in 2026. This opinion was bolstered at the GOMACTech Conference. The primary hurdles today are interoperability gaps, and we believe a storefront FPGA chiplet is a logical solution for a programmable bridge.

With that, I will turn the call over to Elias for his presentation of financial data.

Thank you, Brian. Good afternoon, everyone.

Total first quarter revenue was $5.1 million. This was up 16.5% from Q1 2025 and up 35.3% from Q4 2025. Revenue was approximately $450,000 below the midpoint of our guidance due to a delay in the award of a certain contract that we finalized last week. Revenue recognition for this contract will be ratable and will now extend through Q1 2027 versus through Q4 2026. This shift forward in revenue recognition does not impact the full year revenue outlook that Brian shared earlier.

New product revenue in Q1 was $4.3 million and mature product revenue was $0.8 million. New product revenue was up 14.2% from Q1 2025 and up 50.7% compared to Q4 2025. Mature product revenue was up 31.7% compared to the first quarter of 2025 and down 14.2% from the fourth quarter of 2025.

Non-GAAP gross margin in Q1 was 39.6%. This was below our outlook of 45%, plus or minus 5%. The shortfall was due to inventory reserves of about -- $298,000. This compares to 45.7% in Q1 2025 and 20.8% in Q4 2025. Non-GAAP operating expenses in Q1 were approximately $3.3 million. This compares to $3 million in Q1 2025 and $3.5 million in Q4 2025. Q1 2026 non-GAAP net loss was $1.3 million or a loss of $0.08 per share. This compares to a non-GAAP net loss of $1.1 million or a loss of $0.07 per share in Q1 2025 and a non-GAAP net loss of $2.8 million or a loss of $0.17 per share in the fourth quarter of fiscal 2025.

The difference between our GAAP and non-GAAP results is mainly related to noncash stock-based compensation expenses. Stock-based compensation for Q1 was $858,000 compared to $904,000 in Q1 2025 and $744,000 in Q4 2025. Restructuring costs were $11,000 in Q1 2026 compared with $141,000 in Q1 2025 and $0 in Q4 2025. For the first quarter, two customers accounted for 10% or more of total revenue.

At the close of Q1, net cash was $6 million. This compares with $3.8 million in net cash at the close of Q4 2025. This increase of $2.2 million in net cash is inclusive of $3.2 million raised with our ATM during Q1 2026.

Now moving to our guidance and outlook for our second fiscal quarter, which will end on June 28, 2026. Based on backlog and customer forecasts, our total revenue guidance for Q2 is $6 million, plus or minus 10%. We expect total revenue to be comprised of $5.2 million in new product revenue and $0.8 million in mature product revenue. We anticipate an increase in mature product revenue during the second half that drives the full year total to approximately $4 million.

Based on the anticipated Q2 revenue mix, non-GAAP gross margin for the second quarter is expected to be approximately 42%, plus or minus 5%. As I noted in our last conference call, there are several factors weighing on our non-GAAP gross profit margin during the first half of 2026. For the full year, we're still modeling a non-GAAP gross profit margin of approximately 57%. Please note that given the nature of our industry, we may occasionally need to classify certain expenses to COGS versus OpEx or capitalize certain costs. These classifications are related to labor and tooling for our IP contracts. This may cause variability in our quarterly gross margins and operating expenses that will usually balance out on the operating line.

With that in mind, our Q2 non-GAAP operating expenses are expected to be approximately $3.3 million, plus or minus 5%. We are still expecting full year non-GAAP operating expenses to be approximately $13.5 million. This forecasted growth of approximately 14% in non-GAAP OpEx over 2025 is to support our anticipated 50% to 100% revenue growth in 2026 that Brian mentioned earlier.

After interest and other income, we are forecasting a Q2 net loss of about $800,000 or a loss of approximately $0.04 per share. Based on our current outlook, we anticipate non-GAAP profitability for the second half of 2026. The main difference between our GAAP and non-GAAP results is related to non-cash stock-based compensation expenses. In Q2, we expect this compensation will be approximately $900,000, which is similar to Q1 2026 and Q2 2025. As a reminder, there will be movement in our stock-based compensation during the year, and it may vary quarter-to-quarter based on the timing of grants.

We raised approximately $6.4 million in net proceeds during Q2 2026 using our existing ATM. Based on our current outlook, we do not anticipate further sales using our existing ATM during the balance of fiscal 2026. Excluding money raised with our ATM, we anticipate Q2 cash use of approximately $500,000. Inclusive of money raised with our ATM, we anticipate closing Q2 with just under $12 million in net cash. Please note that our cash use could vary based on the timing of certain payments and receipts from contracts during the quarter. Based on our current outlook, we anticipate positive cash flow during the second half of 2026.

As reported in our 8-K filed on April 30, 2026, we have secured a new banking partner. With this new agreement and considering the amount we have raised with the ATM, we intentionally lowered our credit line to $10 million and secured more favorable terms that will lower our borrowing costs.

I want to thank you for your time. And with that, I will now turn the call over to Brian for his closing comments.

Thank you, Elias. The entire QuickLogic team has worked very hard to accomplish numerous tangible milestones that have set the stage well for 2026 and beyond. This execution, along with the strategic investments and strong customer alliances are the driving forces for the revenue growth we are forecasting to begin this year.

The most significant investments have been our development of eFPGA hard IP for Intel 18A technology and the tape-out of our first RadDPro FPGA test chip. These internally funded investments have provided us with unique positioning in the market and have enabled us to develop close alliances with strategic customers that we believe will benefit QuickLogic for years to come.

With our first RadDPro FPGA in hand, we have already received numerous orders for our RadDPro dev kits for evaluation. Shipment of these dev kits will make a low six-figure contribution to our Q2 revenue. This positions us very well to address applications for various levels of radiation hardened discrete FPGAs and eFPGA hard IP for customer ASIC and SoC designs.

Our early investments to become the first and as it stands today, only company to offer eFPGA hard IP for Intel 18A has also enabled us to build strong customer alliances. One of these customers has already awarded us four contracts with a fifth anticipated during the second half of 2026. Through these contracts, we expect to receive our allotment of test chips that will enable us to fully characterize the performance of our eFPGA hard IP on Intel 18A.

With these data in hand, I believe we can accelerate new contract awards for DIB and commercial applications. This customer also funded the 1 million LUT on Intel 18A feasibility study that led us to implement a number of architectural enhancements. These enhancements have expanded our SRAM to include the lucrative markets for very high-density discrete FPGAs and eFPGA hard IP blocks in ASIC and SoC designs.

In addition to the many initiatives I've outlined today that are designed to power our long-term growth, we are planning three multi-project-wafer or MPW tape-outs this year. All three tape-outs are for chips that we intend to sell via our storefront program. And as I mentioned earlier, the cost for two of these tape-outs will be fully covered by customer contracts that are already on the books. We believe the third tape-out will be covered at least in part by a customer contract.

Our strong outlook for 2026 is based largely on the foundation we built during the preceding years. As I hope we have articulated well during this call, the QuickLogic team is intensely focused on the continued execution of the strategic milestones that we believe will fuel our growth and profitability for years to come.

With that, we will now open the call for questions.

[Operator Instructions] Our first question is from Richard Shannon with Craig-Hallum Capital Group.

Apologies, I'm in transit and hopefully, the ambient noise isn't too bad here. I guess my first question, Brian, is you talked about your customers that are ordering and taking in the test chips, I think you called the RADPro dev kit here. They're going to take most of the year to do this year. I just want to make sure that we're -- that's well within the timing to hit some key programs. I'm sure these are intended for. I just want to get some assurances that's not at risk in any way.

Yes, Richard, we've modeled out some of these key programs that we've been designing this chip for from day one, and it aligns well with those. I'll remind everybody that's why we actually invested in funding our own test chip is to make sure that we did have chips out in time on dev kits to meet within that evaluation window, and we feel like we are within that window. And thrilled to see the uptake of both the orders and the request for pricing and lead times of the dev kits coming out of the HEART Conference.

What do you expect to be the next steps with these customers? Just help us understand what to expect next? What are those milestones to look for?

I mean there's numerous milestones to get to getting designed into an architecture. But I think from the outward-facing milestones that we can talk about throughout this year, people will be doing their own functional evaluation of the tools, of the devices, perhaps their own radiation testing along with us doing that. And then like I said on the call, by the end of the year time frame, that's when we expect to start getting some feedback from people on interest in designing us into these architectures for hopefully programs of record and even ones that aren't out there yet. That lines up well with what we think will be the schedule for our next chips coming off this whole initiative. And we're tracking those schedules very detailed, as you can imagine, to line up architecture, finish and then need of new silicon in the 2027 time frame.

Okay. That's good to hear, Brian. I wanted to ask a question on Intel 18A here. It sounds like you had some great progress with one particular customer. I think you mentioned as a DIB here. I guess I'd love to get a sense of what kind of breadth you're expecting or hoping to see in that node, which I understand is being promoted broadly by the U.S. government to the DIBs here. We've heard a lot about one customer. Do we expect to see any more here? What's kind of the pipeline for expansion with Intel?

Yes. We're actually tracking, I would say, a handful of opportunities at different customers, not just this first one. Some of them are looking at the developments that we are doing and some of these architectural enhancements and assessing how they might use that to benefit from those enhancements as well for larger density. Some of the opportunities could be using our smaller density architecture today. So we have several. Like I said, it's a handful.

So I think we are going to expand on that at some point this year. And I've said this publicly, I'll reiterate it here. It's not just the defense industrial base that is looking at Intel 18A from our perspective for eFPGA, it's actually into the commercial side. So we are targeting a commercial win this year as well for our IP on that node.

Okay. That's good to hear, Brian. Let's hear. Unless I missed something here, I didn't hear any comments specifically about the revenue growth profile you mentioned in the last earnings call for this year, that being 50% to 100%. If you did, I apologize for that. But I just want to get an update thought process on how -- what the profile of the year looks like given the guidance here? Unfortunately, I haven't been able to update my model, so I don't have an overly intelligent way of asking this question. But if you could just kind of give me the top down about how you're going to approach that? And are you thinking of anything meaningfully towards the low end or high end of that number?

No. In fact, the -- you probably weren't logged in yet, but the first sentence I said after welcoming everybody was the progress we've made towards delivering on that 50% to 100% revenue growth target for the year. And if you think about what we did in Q1 plus our guide for Q2, that's already 80% of last year, just in the first half of this year. So we're still tracking to be within that range. You could probably surmise it's moving up in that range now since we're halfway through and we're guiding for what would be a total of 11 in the first half versus 13-point something last year. So I think we're making really good progress on that, really on all fronts on the IP side with 18A, thrilled to get the test chips and dev kits out for the RadPro for FPGA because that's a huge uplift there.

And then also just on some of these new proposals we talked about earlier on different chiplet initiatives, storefront initiatives and then bolstered by some of our mature business being stronger in the second half than the first half. So we're feeling good about being in that range that we talked about entering the year.

Okay. Perfect. Thanks for doing all that math for me. I will do that offline and ask some better questions later, but thanks for that, Brian. Last question, probably for Elias here on gross margins. What are the dynamics here driving the gross margins from, I think, kind of the 40-ish range here to the 50 -- what did my notes say, 57% for the year, that implies pretty healthy levels for the second half year. Just want to get a sense of the dynamics driving that Elias.

Yes. As you know, Richard, I've said this so many times, it's the most difficult one to gauge, the gross margin in this company up and down and different. But the way I'm looking at it is that there's going to be more higher gross margin mix in the second half than in the first half. So for example, when you have certain professional services, for example, they bring in lesser gross margin than the IP itself or the product itself that you're selling. So as you increase that in the second half, to Brian's point, that we're going to have to see something in the second half, that gives you the comfort that the gross margin should be up there. I still want to shoot for 57%. Now if it comes at 55%, nobody should shoot at me with errors, but I mean that's a pretty good bump from last year.

Our next question is from Tyler Burmeister with Lake Street Capital Markets.

I guess I wanted to ask maybe on the U.S. government Strategic Radiation Hardened program. You received a $13 million last tranche end of last year, beginning of this year. Any updated thoughts on potential for additional funding tranches from that program later this year?

Yes, definitely. So we had talked previously, I think or shared publicly that, that $13 million tranche, we're expecting to fully recognize this year as we're continuing on our developments of these next chips. And I think there -- you could assume that we would probably be getting another contract by the end of the year to continue that even further into 2027 and sort of round out the necessary things to complete it. Yes, we didn't really give a lot of airtime directly to that on the call just because things are going fine, and we'd already said it would be recognized fully this year. So it's sort of just a matter of fact.

Perfect. Perfect. I guess that kind of already answers my next question, but then that would, I think, imply that the final chip design with that program remains on track for later this year.

I wish I could share more programmatic details on that. I'm not allowed to. So I'm not going to do that here, but we're -- let me say we're comfortable with the way we're executing.

Perfect. All right. And then maybe pivoting over to your RadPro Development Kits. I think you said several of them had shipped so far. Is that with one customer, multiple customers? Any way to maybe think about the diversity of the customers so far?

It is multiple. I'll start with that. And I'd say the frequency of inbound interest for it has picked up now that we've been able to talk more about it in sort of forms that matter like the HEART Conference. And there's like -- there's a slew of these, let's call them, government, defense, radiation-oriented type conferences. They tend to be a little bit more boutique in nature than something like Design Automation Conference or Embedded Systems. But the quality of leads that we engage with there is high because it's very focused. And coming out of HEART, there was a lot of interest for the dev kits. We're going through that now. We even got messages even today from people saying, "Hey, we're interested, what's the lead time and the cost and stuff like that."

So I think we're going to continue to ship these throughout the year, which is great because that's a leading indicator of, a, interest in something like this; and b, it just gets our software and devices into the hands of these customers and gets them evaluating, which is what we want, right? It's good to see skin in the game from our customers as far as engineering resources, working with our technology.

Perfect. I appreciate that color. Maybe last one for me. I think you explained well the one contract pushout from Q1 to Q2, reiterate the full year to be 50% to 100%. One quarter through the year, that's still a decent range for the full year. Is it possible to call out maybe the couple of biggest potential drivers that could swing that from the low end to the high end? Or is it really just potential timing kind of across the board?

Well, I guess the way I was answering that first question from Richard on the revenue for the year and how it fills in the 50% to 100% growth. I mean the math now with 11% in the first half, like I said, that 80% of last year. So I think we're well on our way to getting into this range that we talked about for the year, the 50% to 100%.

As far as the components of that growth, one is the continued execution on the government contract, which I already alluded to that we're feeling good about that progress. Another was entering the year was to be shipping these dev kits for the RadPro FPGA, which we've started. So that's another, you know, check the box.

We do have in the forecast some 18A, the embedded FPGA hard IP. One, as I mentioned, is for this customer we've already had multiple contracts with and getting this next one for the second half. So that has to be done still, but I think we're feeling good about that. We do have a larger 18A IP contract in the forecast for the year, like a real contract. So to the extent you guys are tracking press releases on this, this would be that commercial customer I'm talking about for Intel 18A embedded FPGA IP. So that would be one that we need to do to be into the upper end of the forecast range.

Like I said, I think we're feeling good about it. Felt great to finally get that one signed that we just signed last week. That's a good milestone to check off the box because that was a fairly large amount of revenue that we're forecasting for the year. Yes, one quarter later, but it's good to get on the books and start executing on that. So not too many more deals to sign to get into the upper half of that range that we talked about.

Our next question is from Neil Young with Needham & Company.

I wanted to start asking on storefront here. So as storefront begins to scale, how should we think about the financial profile? More specifically, should storefront carry a meaningfully different gross margin or revenue recognition pattern once you move from these dev kits and test chips into more of a repeat -- sorry, repeatable product shipments? And then just one more for me after that.

Yes, I can take that one. So storefront is just like the classic semiconductor device business. So we run the supply chain. We sell the device to the customer. It's a revenue and a gross margin at that point in time. Very, very little R&D that goes on top of that because the devices are effectively done. And so the gross margin, a, yes, will be higher. We're modeling like what Elias has historically said on devices like mid- to high 60% for that, like what you would expect in FPGA to be.

But more, I think, more predictable and less up and down because it's less to do with the services and much more to do with just shipping a product, revenue recognized as it goes out the door, gross margin at that point in time because we know the cost of goods, much more predictable.

Perfect. And then the other one I wanted to ask on Quantum Leap solutions. I know you guys put out a press release and you appointed them as authorized sales rep for IP and chiplet offerings. How should we think about the role of that channel in accelerating customer acquisition? Should we think about the bigger opportunities revolving around opening new commercial accounts, sort of deepening the defense aerospace engagement, helping customers navigate chiplet and ASIC integration decisions earlier in the design cycle? Just any color you wanted to throw on that would be helpful.

Yes. I mean, as a company of our size, like most semiconductor companies, which are employees at QuickLogic and then we have our external sales force or indirect. And indirect is usually distributors or sales reps. So in the case of having what I would call design-in products, which are -- you really have to get into your point at the early stages of the architecture, you want sales reps that are sort of focused on that type of technology. So for us, that could be semiconductor IP, it could be EDA tools. It's all of the stuff that ASIC teams typically have to be using because now our sales rep knows those ASIC design groups. And so they can go in. They've already established report, they've established trust and they can expose those groups to QuickLogic technology.

So they've been around for a while. We've known them. We're happy that they've joined QuickLogic. They're not just defense. They also do a lot of commercial. And I think that they have a pretty strong background in helping sell EDA tools, which is great because every ASIC design team that needs IP needs EDA tools. So they know the right people to go to.

So that really helps, gives us leverage in our operating model because that means we have what we call variable costs because most sales reps and distributors are sort of success-based, right? They license -- they help license IP, they help sell devices, they get a commission or a margin on the sale. So it's a fantastic way of aligning what we need as a company with financial incentives for them. And like I said, I think they're doing a great job getting us into people that are beyond or groups that are beyond or numbers of customers that are beyond what we could handle with just our direct sales force today. Does that answer your question, Neil?

Yes.

[Operator Instructions] With no further questions at this time, I would like to turn the floor back over to Brian for closing remarks.

Yes. Thank you all for joining and participating today. We look forward to speaking with you in the near future or on our next earnings call in August, whichever comes sooner. Thank you.

Thank you. This will conclude today's conference. You may disconnect at this time, and thank you for your participation.

Ladies and gentlemen, good afternoon. At this time, I would like to welcome everybody to QuickLogic Corporation's Fourth Quarter and Fiscal 2025 Earnings Results Conference Call. As a reminder, today's call is being recorded.

I would now like to turn the conference over to Ms. Alison Ziegler of Darrow Associates. Ms. Ziegler, please go ahead.

Thank you, operator, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer; and Elias Nader, Senior Vice President and Chief Financial Officer.

As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including, but not limited to, statements regarding our future profitability and cash flows, expectations regarding our future business and expected revenue growth and statements regarding the timing, milestones and payments related to our government contracts.

Actual results may differ due to a variety of factors, including delays in the market acceptance of company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenues, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low power, competitive pricing and short time to market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters and other business interruptions that could disrupt supply or delivery of or demand for the company's products and changes in tax rates and exposure to additional tax liabilities.

For more detailed discussions of the risks, uncertainties and assumptions that could result in those differences, please refer to the risk factors discussed in QuickLogic's most recently filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information, which speak as of the respective dates of any new information or future events.

In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR web page that provides current and historical non-GAAP data. Please note, QuickLogic uses its website, the company blog, corporate X account, Facebook page and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR web page shortly after the conclusion of today's earnings call.

I would now like to turn the call over to Brian. Go ahead, Brian.

Thank you, Alison. Good afternoon, everyone, and thank you all for joining our fourth quarter 2025 conference call. While certain contract delays over the course of the year resulted in much lower-than-expected 2025 revenue, we accomplished numerous tangible milestones that set the stage well for 2026 and beyond. Underscoring this is our forecast for nearly 50% sequential revenue growth in Q1, large contracts for very high-density eFPGA Hard IP cores that are in late stages of negotiation and the acceleration of our storefront business model, which we believe will drive a meaningful revenue contribution beginning in 2026. I'll take a few minutes now to update you on these and other accomplishments.

In our February 18 press release, we announced QuickLogic was awarded a $13 million tranche for our ongoing contract with the U.S. government that was initiated in 2022. We will begin recognizing revenue from this tranche in Q1. In line with my comments during our last earnings conference call, this tranche funds increased quarterly revenue recognition relative to 2025. In parallel with our U.S. government contract, QuickLogic internally funded the development of an SRH FPGA test chip. Last August, we delivered design files to GlobalFoundries to fabricate our SRH FPGA test chip using its 12LP process. This chip was designed to meet the specific requirements of certain large DIBs that have programs in development today that are good candidates for this device. This investment positions us very well as the only source available today for a U.S. fabricated FPGA that addresses the full spectrum of radiation hardness requirements.

We received our SRH FPGA test chip samples earlier in Q1 and announced in a January 14 press release that we have received orders for our SRH FPGA dev kit that enables DIBs to evaluate the test chips. I view this as a strong demand signal and our first tangible step towards what I believe will be hundreds of millions of dollars in potential storefront business for our discrete SRH FPGA during the coming years. Beyond the discrete SRH FPGA market, we are leveraging this test chip to cast a much broader net. In addition to the applications that require strategic radiation hardness that are most likely to design using our storefront discrete SRH FPGA, there are many other applications with less rigorous radiation requirements that may prefer to integrate our SRH eFPGA Hard IP in ASICs.

DIBs are already using GlobalFoundries' 12LP fabrication process for various levels of radiation hardness in ASIC designs. By demonstrating our SRH FPGA test chip that is also fabricated on 12LP, we are positioning QuickLogic to address both discrete SRH FPGA requirements as well as provide DIBs with the confidence they need to integrate our SRH eFPGA Hard IP in future ASIC designs. In some cases, these DIBs may also elect to utilize our storefront services for their ASIC designs.

The short story here is by leveraging the milestones accomplished in 2025, we believe we are very well positioned to successfully address both discrete and embedded FPGA designs across the full spectrum of radiation hardness requirements. And with the architectural enhancements we implemented last year that are extensible to 12LP, we have significantly expanded our SAM in these markets to include the lucrative applications for very high-density discrete and embedded FPGA.

During our last conference call, I stated that a mid-7-figure eFPGA Hard IP contract leveraging Intel 18A was pushed into 2026 due to a delay in government funding. Based on our conversations with this DIB, we remain highly confident we will be awarded this contract once it is funded. While the timing of funding remains uncertain, our discussions with this DIB have expanded to include the potential of QuickLogic providing storefront services for the customer-designed ASIC that will include our eFPGA Hard IP. We expect that we will learn more about the potential expansion to storefront and the timing for this award in the coming months.

During this funding delay and the discussions about expanding the scope of our participation, we have worked closely with this DIB on a variety of projects. Through these efforts, we have been awarded 3 smaller Intel 18A contracts that total well over $1 million, and a fourth is pending that will bring the total to nearly $2 million. The first 2 contracts were for Intel 18A test chips. We delivered IP for both in 2025 and expect to receive an allotment of test chips for our internal evaluation next quarter.

The third contract was for a 1 million LUT feasibility study that we completed in Q4. A fourth contract, which we anticipate being awarded yet this quarter, leverages the architectural enhancements developed during the 1 million LUT study. In support of this contract, we will deliver Hard IP for a very large Intel 18A eFPGA core, the customer plans to integrate into its ASIC that is targeted for tape-out during the second half of 2026.

The architectural enhancements we developed in support of the 1 million LUT study can be leveraged across all advanced fabrication nodes, which we define as 12 nanometers and smaller. These enhancements reduce power consumption, increase performance and reduce the silicon area required for a given size block of our core FPGA technology. In industry terms, the enhancements materially improve our PPA.

With these architectural enhancements in place, we can address the lucrative markets that require very high-density eFPGA cores in ASIC designs and very high-density discrete FPGAs. This significantly expands our SAM for eFPGA Hard IP and discrete devices, including our SRH FPGA, chiplets and other storefront opportunities. In addition to these DIB contracts, we are working closely with a large commercial customer on a new Intel 18A contract valued at several million dollars. We originally expected this contract would be awarded in late Q4. However, the customer decided to expand the size of the eFPGA core in their ASIC to provide greater programmable flexibility. While this is a beneficial trend for QuickLogic, it has delayed the contract award. We are currently forecasting this contract will be awarded during Q2.

During our November 2025 conference call, I stated that we would soon announce the expansion of our involvement with a DIB that specializes in cybersecurity for strategic and tactical weapon systems. On December 8, we issued a press release announcing Idaho Scientific selected our eFPGA Hard IP for forward-leaning hardware-based cryptographic solutions designed to address mobile, IoT, infrastructure and defense systems. Idaho Scientific has a rich history in leveraging FPGA technology to deliver robust security systems that can adapt quickly to changing external threats without the vulnerabilities that are inherent in software-based solutions. By integrating our eFPGA Hard IP into its secure System on Chip processors, it can further enhance its cryptographic security and address new markets much more quickly and with lower risks and lower costs.

Last April, we announced an eFPGA Hard IP contract with a new defense industrial-based customer valued at $1.1 million that will be fabricated on the GF 12LP process. This application utilizes a large block of our eFPGA Hard IP for critical functions, which is a trend we are seeing in designs targeting advanced fabrication nodes. With the cooperation of this DIB and its end customer, we are leveraging the large eFPGA core into a new 7-figure contract that we expect to announce this year. However, due to the fact this contract involves multiple parties, it is taking longer than we expected to finalize. Based on current forecast, we anticipate the contract award later this quarter.

In the scope of this new contract, we will be provided with test chips that we will incorporate in an evaluation kit. The evaluation kit, which is currently scheduled for late 2026, will be compatible with common third-party development environments used by both DIBs and commercial customers. This enables these customers to accelerate system-level evaluations and designs that can use either a storefront version of the discrete FPGA or our eFPGA Hard IP in an ASIC. In parallel with these efforts, we're exploring the potential to leverage the FPGA as a chiplet that is co-packaged with one of our partners' microcontrollers. We are already seeing interest from some of our partners on this concept.

We completed the initial phase of our digital proof-of-concept chiplet program in 2025 as a strategy to accelerate our storefront chiplet initiative. Internally, we refer to this as POC. With the support of our large strategic partners, we leveraged our existing eFPGA Hard IP and readily available third-party IP to move this program forward rapidly and with minimal investment. With ongoing debates regarding the communications and protocol layers of chiplet interfaces, this POC and our decades of experience in FPGA bridging positions us well as a potential solution to move chiplet designs forward to satisfy what appears to be significant pent-up demand.

We were invited to present a paper on our POC at the recent Chiplet Summit and at the Intel Foundry's partners' presentation at the upcoming GOMAC together with Cadence and Trusted Semiconductor solutions. The net takeaway from our presentation at the Chiplet Summit supports our optimism that chiplets will build traction in 2026. The primary hurdles today are interoperability gaps, and we believe a storefront FPGA chiplet is the logical solution for a programmable bridge.

Earlier this year, Epson gave us permission to share its case study that supports our claims that using FPGA technology to process algorithms lowers power consumption without sacrificing programmability relative to processing and software. We published the results in a blog post on January 13. Epson's SoC was originally architected to run workloads entirely in software. But as demand for more features and real-time responsiveness grew, power consumption became a limiting factor.

Epson's engineering team recognized that moving compute-intensive functions into dedicated hardware could deliver significant efficiency gains, but the hardware solution would need to be capable of adapting to changes in algorithms. This meant the only practical solution would be an eFPGA core integrated inside the SoC. By using our proprietary Australis eFPGA IP Generator, we were able to quickly deliver a customized Hard IP core specifically designed to the SoC application that targeted TSMC's e12n fabrication technology. Adding to our challenge was the fact that this would be our first eFPGA Hard IP for e12n.

From design handoff to silicon validation, the IP integrated cleanly into Epson's SoC without the need for re-spins or late-stage design changes. Epson was able to boot, configure and validate the eFPGA subsystem immediately, accelerating its schedule and reducing risk. After final testing, Epson confirmed the resulting design, reduced overall power consumption by 50%. This makes a huge difference for battery-powered systems. Given our success in this design, we believe we are very well positioned for future opportunities with Epson as well as other companies with similar requirements.

As I'm sure you noticed in our 8-K, we took a large impairment charge on SensiML. This is due to the standard accounting practice to impair the value of an asset held for sale for a year or longer. During the last year, we have discussed the divestiture of SensiML with microcontroller companies. And in one case, those discussions advanced to due diligence, but were concluded without an agreement. We are in discussions today with a large company where SensiML software potentially presents high value for new AI and drone projects. We cannot provide assurance that this or other discussions will result in a transaction.

With that, I will turn the call over to Elias for his presentation of financial data.

Thank you, Brian, and good afternoon, everyone. Total fourth quarter revenue was $3.7 million. This was down 35% from Q4 2024 and up 84% from Q3 2025. New product revenue in Q4 was $2.8 million and mature product revenue was $0.9 million. New product revenue was down 39% from Q4 2024 and up 199% compared to Q3 2025. Mature product revenue was down from $1 million in the fourth quarter of 2024 and $1.1 million in the third quarter of 2025.

Non-GAAP gross margin in Q4 was 20.8%. The primary reasons the non-GAAP gross profit margin was below my outlook are $473,000 in inventory reserves and $135,000 in contracted professional services costs attributable to COGS that were not anticipated at the time of our last conference call. The balance is mostly attributable to a higher-than-expected contribution from professional services relative to IP and mature product revenue.

Non-GAAP operating expenses in Q4 were approximately $3.5 million. This was $500,000 above the midpoint of our outlook due to the booking of certain executive incentives in Q4. This compares with non-GAAP operating expenses of $2.9 million in the fourth quarter of 2024 and $2.9 million in the third quarter of 2025. Non-GAAP net loss was $2.9 million or $0.17 per share. This compares to a non-GAAP net income of $0.6 million or $0.04 per diluted share in Q4 2024 and a non-GAAP net loss of $3.2 million or $0.19 per share in the third quarter of fiscal 2025. The difference between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses and the noncash impairment charge for SensiML that Brian mentioned.

Stock-based compensation for Q4 was $700,000 compared to $900,000 in Q4 2024 and $800,000 in Q3 2025. For the fourth quarter, 3 customers accounted for 10% or more of total revenue. At the close of Q4, total cash was $18.8 million, inclusive of $15 million from our credit facility. This compares with $17.3 million, inclusive of $15 million from our credit facility at the close of Q3 2025. This increase of $1.5 million in net cash is inclusive of $3.2 million raised with our ATM during Q4.

Now moving to our guidance and outlook for our fiscal first quarter, which will end on March 29, 2026. Based on backlog and customer forecast, our total revenue guidance for Q1 is $5.5 million, plus or minus 10%. We expect total revenue to be comprised of $4.5 million in new product revenue and $1 million in mature product revenue. For the full year, we anticipate mature product revenue will be approximately $4 million. Based on the anticipated Q1 revenue mix, non-GAAP gross margin for the first quarter is expected to be approximately 45%, plus or minus 5%. For the full year 2026, we are modeling a 57% non-GAAP gross profit margin. However, there are several factors that we believe will weigh on our non-GAAP gross profit margin during the first half of 2026.

We are modeling services revenue will be a high percentage of total revenue during the first half. In support of services, we will have costs for software tools that we lease, and we will utilize outside engineering services in addition to our internal resources. A large percentage of these costs are currently being modeled as COGS. We expect some percentage of these costs will be capitalized, but it is unclear at this point the exact percentage. Also during the first half, we will incur certain significant costs associated with large contracts that will be recognized late during the quarter and the offsetting revenue will not be recognized until the following quarter. We're modeling these factors as negatively impacting our non-GAAP gross profit margin during Q1 and Q2.

Among the significant costs we are modeling for fiscal 2026 are 3 multi-project wafer or MPW tape-outs. All 3 tape-outs are for products that we intend to sell via our storefront program. The costs associated with 2 of these tape-outs will be fully covered by customer contracts. One of these contracts is already on the books and another is in the very late stages of negotiation. We believe the costs associated with the third tape-out will be covered at least in part by contracts. If contracts are secured in advance of this tape-out, it would be an upside to our full year model.

Please note that given the nature of our industry, we may occasionally need to classify certain expenses to COGS versus OpEx or capitalize certain costs. These classifications are related to labor and tooling for IP products -- IP contracts, pardon me. This may cause variability in our quarterly gross margins and operating results that will usually balance out on the operating line.

With that in mind, our Q1 non-GAAP operating expense is expected to be approximately $3.2 million, plus or minus 5%. We are expecting full year non-GAAP operating expenses to be approximately $13.5 million. This forecasted growth of 14% in non-GAAP OpEx over 2025 is to support our anticipated revenue growth in 2026. After interest and other income, we are forecasting a Q1 net loss of about $800,000 or a loss of approximately $0.04 per share. The main difference between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses. In Q1, we expect this compensation will be approximately $800,000, which is similar to Q4 2025 and Q1 2025. As a reminder, there will be movements in our stock-based compensation during the year, and it may vary quarter-to-quarter based on the timing of grants.

Prior to this conference call, we raised approximately $3.2 million during Q1 using our existing ATM. We anticipate Q1 cash use net of money raised with our ATM will be approximately $1.4 million. Our projected Q1 cash use is negatively impacted by the expected timing of payments attributable to our prime U.S. government contract. The timing of these payments during the year are expected to benefit cash flow during the second half. As a heads up, we are working to secure a new banking partner as we are focused on obtaining more favorable terms that will lower our costs and purposely reduce our line of credit from $20 million to $10 million.

Thank you for your time. And with that, I will now turn the call over to Brian for his closing comments.

Thank you, Elias. Through hard work, dedication and long hours, the QuickLogic team accomplished numerous strategic milestones in 2025 that has enabled us to enter 2026 on extremely sound footing. Thank you all for what you have accomplished. Our continued performance on our prime U.S. government contract has led to its expansion to a potential $89 million. The addition of GlobalFoundries and its 12LP fabrication process, which is used today by numerous DIBs for a variety of radiation hardness requirements and most recently, the award of a $13 million tranche.

Independent of this contract, QuickLogic funded its own strategic radiation hard or SRH discrete FPGA test chip. We now have test chips in hand as well as orders for our SRH FPGA dev kit that will enable DIBs to evaluate our test chip for the full spectrum radiation hardness requirements. This significantly accelerates our ability to win both discrete SRH FPGA designs we can storefront as well as designs that are better suited to embed our SRH eFPGA Hard IP in ASICs.

To further accelerate our storefront business model in 2026, we are planning 3 multi-project wafer or MPW tape-outs this year. All 3 tape-outs are for chips that we intend to sell via our storefront program. The cost for 2 of these tape-outs will be fully covered by customer contracts. One of these contracts is already on the books and another is in the very late stages of negotiation. We believe the third tape-out will be covered at least in part by contracts.

Through a revenue-generating contract with a customer, we developed architectural enhancements for our core eFPGA technology that enables us to address the lucrative markets for very high density in both discrete and embedded designs. These enhancements were initially developed for Intel 18A and are extensible to all advanced fabrication nodes. Given the sound foundation of the recently awarded U.S. government contract, our outlook for continuing mature business of approximately $4 million in 2026 and the number of pending contracts that are in the late stages of negotiation, we believe we are well positioned to deliver between 50% and 100% revenue growth in 2026.

With that, I will turn the call over for questions.

[Operator Instructions] Our first question is from Richard Shannon with Craig-Hallum Capital Group.

Brian, you kind of saved the best for last year with the outlook for the year here. So I guess I'll start with that topic here and ask for a little bit of help in trying to think about the dollar growth here contributions as we go from '25 to '26 in that 50% to 100% here. I wonder if you could tray that by SFR contribution, defense versus commercial and any other ways you'd like to split that up, please?

Sure. So as I said, $4 million of that is going to be our base mature business, which we're very comfortable with at this point for the year. And then, of course, the $13 million tranche for the U.S. government contract, so that's $17 million. If you were to look at the range of 50% to 100%, obviously, we need to get well into the 20s to get to that. And we're expecting that there will be additional contracts that are defense related for either the one of those MPW test ships that I alluded to and/or IP that would be to defense contractors for use in their ASICs.

As I mentioned, as we've gone and upgraded our architecture to support higher LUT counts, we're seeing a lot of interest in that type of architecture for some of these process technologies that are tried and true for U.S. defense companies like 18A and 12LP. And then if you go on top of that a little bit further, we see other commercial IP opportunities, one of which I mentioned during the call that we felt was pushed into 2026 from 2025 with that commercial customer specifically because they were looking at making the IP core larger to handle more capability. And so there was a lot of architectural discussions and trade-offs going on that sort of naturally pushed that IP contract into what we're now forecasting to be 2026. But that would be a nondefense customer for that particular IP license. Does that give color to the question, Richard?

Yes, it does here. So maybe -- I probably should have asked this as a multiple-part question here, but maybe I just want to get a little sense of what are the differences between the high and low end of that range here. I think I heard part of it, but I'd love to hear you put that all together, please.

Sure. So the -- if you look at the low end of that range, that would definitely be the base $4 million business, the current tranche that we have for the government contract and I'd say a couple of IP licenses, one of which would be useful for one of these MPW tape-outs. And then the higher end or even exceeding the higher end of that would be as we layer additional IP licenses on top of that and perhaps even further funding on the government contract.

Okay. That is helpful. Maybe a couple of other questions for me here. So big picture, when we look at strategic rad-hard, both -- I asked this question both as FPGAs as well as the opportunity to storefronts for ASICs to include your IP here. What do we think -- or how do we think about timing of wins with any of these DIBs for, I think, substantial programs that I think was the intention of this program all along here. Help us understand what you're expecting to happen this year versus in the following years.

So this year, we're expecting evaluations to take place using our test chips, either ours or the government-funded one and then getting to some sort of architecture understanding with these DIBs by the end of this year, this fiscal year, next year, starting actual development activity with those chips. So to be clear, this year is very much an evaluation year. All of these companies are very risk-averse from a technical perspective. And so they need the time to dig into the test chip and make sure that they understand it and are comfortable with the tools that go along with it, meaning our software tools and the device and the dev kits themselves. So meaning exiting this year with their positive feedback and sort of thumbs up that they want to move forward with architecture insertion next year.

Okay. That is helpful perspective. Maybe jumping back quickly to the thought process for the year here. You mentioned a sales number and then Elias also gave us some other numbers. I wasn't able to put those together here to understand whether we're going to be net income positive or cash flow positive this year. Maybe you can help us understand your thought process either both at the low and the high end of your sales guidance range.

Well, I'll tell you if it's -- we're expecting cash flow positive on the second half of the year for sure, not the first half, Richard.

Okay. And how about net income or EPS? What's that looking like on the bottom line?

Same. I think we'll be on the high end in the second half of the year and not the first half as well. But I expect to be both positive on net income in the second half of the year.

Okay. That is helpful. And one last question for me, and I'll jump out of the line here. Brian, you mentioned targeting 3 MPWs this year. And I think I've lost a couple or some of the details you offered regarding that. But maybe you can help us understand the dynamics here? And is this something that's kind of follow-on to the ones you got on last year? Or are these blossoming opportunities that you expect to continue to do here? Like how should we think about these? And I can't remember also, did you mention the process node or even foundries that those would be on.

Yes. We did not mention process technology for these, and I'm not going to. But they are based on process technologies that we already support. So we don't have to do an actual physical port to a new process to execute on these. And I think we're trying to convey that 2 of these will be fully covered by customer contracts and one of them would be partially covered by the contract. The key here being that there's going to be end customers associated with all 3 of them. They are the driving force behind the definition of these. And in some cases, like we mentioned, either partial or fully funding the development of them during the year.

Our next question is from Neil Young with Needham & Company.

The first question, I wanted to ask about the high-performance data center win that you talked about in the press release. Maybe if you could dig a little bit deeper on that, share what the application is? Just any other color, I think, would be interesting.

Sure. So this is a 12-nanometer design, and it's for an eFPGA IP core. The eFPGA IP core for this particular one is a meaningful percent of the die size, meaning it's not just an insurance policy, it's actually delivering capability that they've architected in from day 1 to be very important for the functionality of this chip. Because it's not a 3- or 4-nanometer chip, obviously, it's not going to be a GPU class device. But there's a lot of peripheral components in these data center printed circuit boards that surround those types of devices. And this would be an example of one of those, let's call it, peripheral chips that are still important and critical for overall functionality, but not at the core of the compute. So we're continuing to execute on that, continuing our engagement with the customer and hopefully supporting their tape-out at some point later this year.

The nice thing about it -- I'm glad you brought it up, Neil, because this is sort of the -- probably the largest IP contract we've had in recent times for a nondefense application. And a lot of people have asked us repeatedly, are you going to be beyond just defense? And we said, yes. And I think it's glad that we're able to talk about this particular example because it clearly is a nondefense application, and we believe hopefully the start of other nondefense applications as well. The other one I'll mention is Epson, right? We gave Epson more airtime today in the call based on that blog. That's also an example of a nondefense use. So it's been a while getting to more commercial customers, but I think we're starting to see a little bit more momentum and interest there now that we have these other process technologies supported.

That makes sense. The other question I had, I'm just interested in the competitive dynamics. So you talked about the potential storefront business being pretty large for this discrete strategic rad-hard FPGA during the coming year and the year after that. I was curious if the competition differs at all from your traditional eFPGA IP that you've talked about. So just anything different on the competition front would be helpful, just understanding that.

Sure. So if we go up to 50,000 feet and we say, what's the programmable logic umbrella in total, there's eFPGA and there's FPGAs. And most people know the FPGA competitors, or I guess, the peers, if you will, some of them not really competitors, would be Xilinx and Altera and the FPGA division of Microchip and Lattice and Efinix and Achronix. Those are sort of the companies that do discrete FPGA devices.

Now of those, if we think about what are the ones that are U.S.-based and have a defense focus and [ 2 ] devices that would fall into this category of some level of radiation hardness, you can kind of go and zoom in and say, okay, well, today, Microchip has devices from their Actel acquisition long ago that do this rad-tolerant, to some extent, rad-hard. Xilinx has some rad-tolerant, I think 1 rad-hard device. I think Altera has some, although I admit I haven't looked at their product portfolio recently. And I think Lattice would like to get into defense and doesn't really have anything today in that area. I don't think Achronix has. I think Efinix is mostly focused on Asia. So you already whittle down pretty closely to just a couple of people that do any level of serious radiation hardness or tolerance.

But when you compare and you say, okay, well, let me move the bar and say, it has to be manufactured onshore and it's got to meet strategic levels. I would challenge anybody to go to the websites of those companies I just mentioned and point to a device that meets those requirements. I think it's an all set. So I think we're really well positioned in that sense as we continue to execute on this program.

Now the other part of the programmable logic umbrella, as I mentioned, is eFPGA IP. And none of those companies that I just mentioned have a real eFPGA IP business. They want to sell new devices because they view IP as undermining device sales, I would imagine. From an IP perspective, there's really just a couple of companies that have done IP in the last few years besides QuickLogic. One is called Flex Logix that was acquired last year by Analog Devices and made captive, so they don't do licensing anymore. And now there is a French start-up company called Menta and they have licensable IP. And then there's a couple of really tiny academically oriented companies that I won't even give airtime to today.

So if you compare us against one company, Menta, again, I go back to we're a more established company. We're doing business with all these big companies. We have the spectrum of IP2 devices. We're a U.S. company, products made in the U.S. So we have a lot of, I would say, differentiation at that level compared to Menta. But the more important one is when you dig into the technical details, Menta is a soft IP company. And so soft IP means that when you're licensing IP to a customer, they're not just getting soft IP, they're getting a big boatload of work to make it a hard IP before they put it into their ASIC. And with that boatload of work comes a lot of risk and time and cost. And when you're a hard IP supplier like we are, we take care of all that. They don't have to worry about designing anything. They just need to think about how do I architect and use this IP.

And so there's a huge difference in the engagement model between us and Menta. And that's, I think, reflected in the wins that we're announcing, who is using us. It's also reflected in the average selling price of our IP, right? We're not doing soft IP that is a $20,000 IP that comes with it a lot of work. You're licensing something for quite a bit more money, but we're taking care of that work and risk for the customer. And that's the huge difference between us and Menta as far as the eFPGA IP goes. Hopefully, that helps as an update on the competitive [ metrics ].

Our next question is from Tyler Burmeister with Lake Street Capital Markets.

So first, great to see the next tranche of the U.S. SRH development program, the $13 million you got as well as the announcement that the program had expanded with GlobalFoundries process. Maybe it's a little bit of a follow-on from an earlier question. I think you said potentially in the high end of expectations this year, you could see more funding. But to the extent you're able to, I'm just wondering, could you give any color on what next milestones we should be expecting or looking forward to from that program?

Sure. I'm asked this question a lot, Tyler. And unfortunately, I can't give programmatic details out on the program. But what I can say is I'll go back to something I was given permission to say when we first got this contract in 2022, which is that the scope of this whole contract contemplates 2 devices, a test chip and a final chip. And so we were able to say, I think it was in December press release when we announced the contract ceiling expansion to $89 million and adding GlobalFoundries that we had, in fact, taped out a test chip for that contract. So you can sort of check one off the list there of the 2.

So you can imagine I think it's a natural extension that with more funding, especially the rate -- the increase in the funding from this year over last year and the fact we've already done 1 but not 2 chips that we're embarking on that second chip development now. And unfortunately, I'm not going to be able to give really specific details on what's in the chip and when we're taping it out and when it's going to come out, but it's all in line with our obligations to the government for this contract.

Yes. That's perfect. I appreciate the extra color there. And then the full year guidance was great, and I appreciate the details around that. Just putting the pieces together, strong Q1 and a number of initiatives kind of coming together at the same time here. Would it be reasonable to potentially expect some lumpiness through the year, maybe Q2 sequentially down? Or do you think you could grow revenue sequentially kind of linearly through the year?

So we actually think that Q1 is going to be the low point for the year, right? We'll give that breadcrumb, that the other quarters will be over Q1. There may be some lumpiness. And the reason why I say maybe is that when you're dealing with contracts that are $2 million, $3 million each, especially if it's IP and it's recognized on delivery, then there's some natural lumpiness to when we get the contract and we make the delivery in a particular quarter, right? So there may be lumpiness from that perspective. But I think we're trying to give this outlook that Q1 is actually the low point for the year, that it's going to be up from here.

Our next question is from Gus Richard with Northland Capital Markets.

Just on Q3, you guys mentioned a $3 million commercial contract that you expected the revenue in Q4, didn't look like you did. Is that part of the guide for Q1?

No, it's not. In this call, we said that we're expecting or forecasting that to be contracted in Q2. And so that $3 million is not part of the Q1 guide. The other thing I'll add, Gus, is when we said initially Q3 and then in Q4, we said it may be in there or not, and it clearly got pushed. This is the one where we had said that now what they're looking at is a larger eFPGA core. And because they're looking at larger cores, they want to basically take more time on the technical feasibility side and diligence before we execute a contract. But it's not in the Q1 guide to be very clear.

Okay. And that contract is upside if I heard you correctly.

I'm sorry, could you...

The value of the contract was increased.

Yes. Well, we said the size of the core has increased. We didn't say the value of it has increased, but the amount of eFPGA logic that they want is definitely larger than what they had originally thought of.

I understand. And then my next question is for the test chip that you guys taped out and have gotten samples back and you're getting orders for the test development boards. When do you expect those to start to ship? And how much revenue do you think you can generate and from how many customers?

Several questions in there. Let me unpack that. So -- and for clarity, we've talked about 2 test chip tape-outs now, right, publicly. We've talked about the government-funded one. We've talked about the self-funded one. So because I can't give updates on the government one by my obligations to the government, I can just talk about our self-funded one. So on the self-funded one, we did receive the chips in Q1. I'd say the fab was a little bit later than what we had planned on for that. Our engineering team is working on those chips right now and going through the validation process.

And what I've said previously is that as soon as we have those validated, then we'll make sure that we can get those out to fulfill the test chip for the dev kit orders. And I think we've said previously, we'd love to get it out by the end of Q1. If it's into Q2, then that's fine, too, because we intentionally did this test chip tape-out. So we gave ourselves a lot of buffer in terms of time for us to get these into the hands of the DIB for them to do the evaluations that they need to do to get comfortable.

And I think your last question, Gus, there was how many customers. So the nature of this type of device being rad-hard means that there aren't a lot of people that you're actually allowed to sell it to, clearly U.S.-based. And the nature of this is really for the strategic defense systems, and there's only a handful of those that actually design for any kind of subsystem in those devices or systems, I should say. So our target is less than 5 because those 5 really, really matter in terms of these major systems.

Got it. And then my last one is on gross margins. How do we think about the trajectory of gross margins going through the year? Non-GAAP 45% for the first quarter, does that step up at all in the second quarter and -- or is it more of a linear ramp? How do we think about that?

Q1, we said 45%, give or take. Q2 would most likely be around the same flattish. And Q3 and Q4, I see an upside big time on gross margins. I have to say, over the time I've been here, this has been the most difficult piece of the puzzle to gauge and forecast, mainly because of the way we capitalize certain COGS and move certain things into OpEx and otherwise. So it's been a very tough exercise to do, but we're getting there. But overall, I see a decent 57% for the full year in terms of gross margin that I said in the script.

Our next question is from Rick Neaton with Rivershore Investment Research.

I just had one question about chiplets. And you're talking about your bridging technology that you've used in the past with programmable logic. How do you see these chiplet applications using programmable logic in what end uses are some of these being contemplated? And when you say -- the second part of the question is on bridging, are you talking about bridging on the chiplet or between chiplets?

Okay. So 2 questions there. One is really the use case, the end applications for chiplets? And then one is, I guess, how are they partitioned within these packages? Is it all resident in one chiplet? Or is it multiple chiplets to solve the problem, right?

Right, right. Are you bridging between layers on a chiplet or are you bridging between multilayer chiplets? I'm just curious.

I think -- yes. No, I can elaborate on some of this. So on the -- let's start with the end markets and use cases for the chiplets. So I think we've talked about this before, but aerospace and defense is a really big market for chiplets because they don't want to have to do a bunch of custom ASICs if they can avoid it because their volumes are not terribly large, and it costs a lot of money to go off and do these custom ASICs. So to the extent they can make things heterogeneous inside the package, it's going to really help offset their program costs for development. So eFPGA in that case, you can almost look at where are FPGAs used today in those systems and that becoming a chiplet and connecting them with other devices that FPGAs interface with in those systems today.

So in those systems today, you generally have some sort of big processor, could be a flight computer. The FPGA technology today is very useful for signals that are coming in from sensors, doing preprocessing on those signals and packetizing them in a way that the actual CPU or SoC can process on without having to redo a lot of that capability that the FPGA is doing. Because remember, FPGAs are very good at real-time, highly parallelized computation. So that's sort of the overall defense use case for these.

And again, you can imagine that there's a lot of software that's already been written in the defense industry for certain processor architectures, there's already a lot of FPGAs used. Packaging those die or capabilities inside one package actually saves on the A and PPA, which is area, right? A lot of these systems are going for more miniaturization and they're looking at packaging these things in a single package to do that. So that's the big use case there.

I'd say outside of defense, there's a lot of interest for security or things that are sort of protected from this post-quantum era of computing for really just protecting systems from a cyber perspective. And eFPGA or FPGA is good for that because in the event that anything is hacked in the future, if the hardware itself is programmable, then you can reprogram whatever algorithm that you have in those to adapt to that threat at the time. And so there's interest in that as far as making these systems more trusted.

And I don't mean trusted from a defense perspective, I mean trusted in the sense that you can trust that it's running what it's supposed to be running and nothing more than that. So that's also an interesting use case that's coming up for eFPGA chiplets. Again, the same idea being they've got a lot of software and infrastructure already. How can they adapt that existing infrastructure by adding a little bit of programmability and not redesigning all the ASICs. So that's a good use for an eFPGA chiplet.

Now as far as the bridging goes, you can see from these examples that we're not replacing the whole SoC with this eFPGA. It's basically taking the capability of a discrete FPGA and getting it inside the same package as what the SoC is or the ASIC is in their system architecture. And then as far as the actual bridging goes, chiplets is kind of like if you go back to when USB or PCI was first being broadly adopted in the PC or laptop era of growth, that sort of happened. That was successful because everybody was able to standardize on a common interface, right? PCI is PCI, USB is USB. You design a peripheral with that, you go to the plug fest, everything works, everybody is happy.

In chiplets, it's a lot more complicated than that because you have these different flavors of UCIe as an example, and you have a bunch of wires, BOW, and they're incompatible. And so there isn't this notion of like universal compatibility. And then if you dig even further into the details, if you want to, there's a difference between the physical layer and the protocol layer, right? So you can imagine like a physical layer is me writing a note on a piece of paper and passing it to you, right? I pass the paper, you receive it, we're all good. But if I'm writing in a different language than what you understand, it's going to look like gibberish when you try to read that paper.

And the same thing is happening with UCIe, where the physical layers may be compatible, right? UCIe cores on both sides, but the protocol that people are putting over UCIe are different. And that's exacerbated by people doing ASICs at different points in time. So one of the things with our eFPGA is we're thinking, well, that hardware is actually programmable. So as long as the physical layers are connecting and as long as you have enough gates in our FPGA, you can probably program them to add some level of compatibility or in my paper analogy like a translator.

And so we're hopeful that some of those will actually come to fruition based on that value proposition. And we're starting to get some positive feedback on that idea based on what we heard at the Chiplet Summit last week, and I think what we're going to hear at GOMAC next week in Louisiana when we're there presenting. Does that help the use cases?

Yes. No, I appreciate the color.

Our final question is a follow-up from Richard Shannon with Craig-Hallum Capital Group.

Just one last question for me. Brian, again, hitting on the topic of strategic rad-hard and actually probably want to extend this maybe to rad-hard given your comments on the call today here. But how many distinct programs are you bidding on here? I know you're not going to tell us an exact number, but I was hoping you could use language like a couple of few, several over a dozen, that sort of thing here. Just help us get a sense of the number of programs you're bidding on.

I would say the immediate ones that are the highest level of radiation hardness, there are less than 5 major programs, but there are several subsystems within each major program that we would like to be inserted into. So I guess you could -- what you hear about there is the total number of socket opportunities in that kind of part of land. And that would be I don't know, 10 to 20 total. And that's for the highest level of radiation, which has been our focus because that's the greatest area of differentiation.

If you start relaxing the radiation hardness requirements, obviously, you can get into a lot of new applications around space. And there's going to be tens of applications in space. But the initial focus, especially for these first dev kit orders is going to be the ones that are the higher levels of radiation where we don't have a competition at this point.

That's great perspective, Brian.

There are no further questions. I would like to turn the conference back over to Brian Faith for closing remarks.

Thank you. And we will provide a technical presentation on our chiplet POC at the Intel Foundry's partners' presentation at the upcoming GOMAC, March 10, together with Cadence and Trusted Semiconductor Solutions. In April, we will exhibit at HEART, which is another government radiation effects-oriented conference and also exhibit and present at IP SoC Days in Silicon Valley, again, in April.

Thank you for your support and for joining us today, and we'll talk with you next time. Thank you. Goodbye.

Thank you. This will conclude today's conference. You may disconnect at this time, and thank you for your participation.

Ladies and gentlemen, good afternoon. At this time, I would like to welcome everyone to the QuickLogic Corporation's Third Quarter Fiscal 2025 Earnings Results Conference Call.

As a reminder, today's call is being recorded for replay purposes through November 18, 2025. I would now like to turn the conference over to Ms. Alison Ziegler of Darrow Associates. Ms. Ziegler, please go ahead.

Thank you, Van, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer, and Elias Nader, Senior Vice President and Chief Financial Officer.

As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including, but not limited to statements regarding our future profitability and cash flows, expectations regarding our future business and statements regarding the timing, milestones and payments related to our government contracts statements regarding the use of the company's ATM program and statements regarding our ability to successfully exit [SNL].

Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue.

Our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, and our ability to introduce and produce new products based on advanced wafer technology on a timely basis.

Our ability to adequately market the low-power competitive pricing and short time to market of our new products, intense competition from competitors, our ability to hire and retain qualified personnel, changes in demand or supply, and general economic conditions.

Political events, international trade disputes, natural disasters, and other business interruptions that could disrupt the supply or delivery of or demand for the company's products, and changes in tax rates and exposure to additional tax liabilities.

For more detailed discussions of the risks, uncertainties, and assumptions that could result in those differences, please refer to the risk factors discussed in QuickLogic's most recently filed periodic reports with the SEC.

QuickLogic assumes no obligation to update any forward-looking statements or information, which speak as of the respective dates of any new information or future events.

In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements.

We have also posted an updated financial table on our IR web page that provides current and historical non-GAAP data. Please note, QuickLogic uses its website, Hy blog, its corporate Twitter account, Facebook page, and LinkedIn page as channels of distribution of information about its business.

Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD.

A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR web page shortly after the conclusion of today's earnings call.

I would now like to turn the call over to Brian. Go ahead, Brian.

Thank you, Alison. Good afternoon, everyone, and thank you all for joining our third quarter 2025 conference call.

We have made very significant progress since our August conference call. Last quarter, I stated that we focused considerable engineering resources to accelerate storefront design wins for our strategic Radot FPGA and expand our served available market to include very high-density eFPGA Hard IP designs targeting advanced fabrication nodes.

I'm proud to say our engineering team has executed beautifully, and we are realizing these goals. We expect to begin recognizing storefront revenue in early 2026, and that it will provide a meaningful contribution to total 2026 revenue.

The interest from large defense industrial-based entities, or DIBs, in the SRH test chip we funded is notably higher than I anticipated. We have significantly expanded our ability to address the lucrative markets for very high-density discrete FPGAs and ASICs that require large blocks of eFPGA.

New contracts and engagements are for much larger blocks of eFPGA and on advanced fabrication processes. The value contribution of eFPGA and customer designs has grown substantially.

Our penetration in commercial market sectors is expanding. And with this progress, the rate of new contract closure is accelerating to the point that license revenue may surpass NRE revenue for the first time this quarter.

We believe these trends will accelerate going forward. Before I get into the tangible data that support these points, I want to take a moment and provide some color for the revenue guidance Elias will share in his presentation.

Based on our backlog and forecast provided to us by our customers, we are targeting a total revenue of $6 million for Q4. The majority of the contracts that support this outlook are already on the books or have been forecasted by customers to be awarded during the coming weeks.

However, a contract valued at nearly $3 million for a commercial application targeting an advanced fabrication node has been forecasted by the customer to be awarded late in the quarter.

If this contract is awarded on or very near the date forecasted, we will be able to recognize a large portion of that revenue in Q4 and, with that, realize our $6 million objective.

We have a very high level of confidence in winning this contract. But note that it could push into Q1 2026, and that would result in lower Q4 2025 total revenue.

Due to this, Elias will present an unusually wide guidance range. And now let's walk through our accomplishments. In early August, we delivered design files to GlobalFoundries to fabricate our SRH FPGA test chip using its 12LP process.

This test chip was designed to meet the requirements of certain large DIBs that have programs in development today that are good candidates for this device.

We expect delivery of test chips in early Q1 2026 and believe we will have our SRH dev kit ready for shipment to customers shortly thereafter. This initiative was financed by QuickLogic and is independent of our contract with the U.S. government.

Our decision to invest the money and resources to develop this test chip was based on our belief that it is critical in our quest to secure strategic design wins and accelerate our storefront business model.

Since our last earnings conference call, I have personally met with a number of the DIBs that worked with us through the development process, and I cannot emphasize enough the potential of our SRH storefront initiative.

In prior meetings, all I had to show were PowerPoint presentations. And now with the test chip in fabrication, the level of enthusiasm is palpably higher.

As a matter of fact, we already have commitments for SRH dev kit orders that we expect to receive by the end of this month. I see this as our first tangible step towards the hundreds of millions of dollars in potential storefront business we could win in the coming years.

The importance of demonstrating our SRH FPGA test chip goes well beyond the storefront designs we believe it will enable us to secure. FPGA is the #1 spend category for semiconductor devices by the defense industrial base, and custom ASICs are a close second.

Together, we believe these 2 categories make up roughly half of the DIB semiconductor TAM. We expect many of the new strategic designs that require various levels of radiation hardness will use either discrete FPGA devices that we can storefront or eFPGA hard IP we can license in new ASIC designs.

By delivering a discrete SRH FPGA test chip fabricated on the 12LP process, we are demonstrating the broader capability of our eFPGA hard IP for ASIC applications that will meet program requirements ranging from radiation-tolerant to strategic rad-hard.

There are 3 very important points I want to highlight here. First, DIBs are already using GlobalFoundries' 12LP fabrication process for radiation-tolerant and SRH ASICs.

Second, government contracts require the use of onshore fabrication for strategic programs when devices are available. As it stands today, we will be the only source for strategic rad-hard FPGAs and SRH eFPGA hard IP that is fabricated in the U.S. by a U.S. company.

Third, in my meetings at large DIBs, engineering managers have clearly stated that being able to design with our Aurora FPGA user tools for both our SRH discrete FPGAs and our eFPGA hard IP and ASIC designs is a huge plus.

During our last conference call, I stated that Q3 would mark the low point for revenue recognition for our U.S. government SRH FPGA contract this year.

Funded by the current tranche, revenue recognition from the contract will rebound significantly in Q4. Beyond that, we anticipate an increase in quarterly revenue recognition in 2026 that will be funded by the next tranche.

During our last conference call, I forecasted the award of a mid-7-figure contract from a DIB during Q4 that targets Intel 18A. Unfortunately, there has been a delay in funding that pushes this contract into 2026.

We are highly confident that we'll be awarded this contract, but at this juncture, our customer has limited visibility on the timing of funding. While we await funding for this 7-figure deal, it is worth noting that we have already been awarded multiple contracts by this strategic customer during 2025.

We delivered customer-specific eFPGA hard IP for this customer's first Intel 18A test chip last April. We expect to receive our allocation of test chips from this contract during Q1 2026 for our internal verification and characterization.

We were subsequently awarded a mid-6-figure contract for a second Intel 18A test chip. We delivered customer-specific eFPGA hard IP for this test chip during Q3.

In addition to these Intel 18A test chip contracts, during our last conference call, I announced that this customer awarded us a contract for a 1 million let feasibility study that we are scheduled to deliver next week.

We are anticipating a follow-on order in the coming weeks associated with this feasibility study that will enable the customer to tape out a very high-density Intel 18A proof-of-concept device during the second half of 2026.

The architectural changes we implemented in this feasibility study can be leveraged across all advanced fabrication nodes, which we define as 12 nanometers and below.

With these changes, we can now address the lucrative markets that require very high-density eFPGA blocks in ASIC design and very high-density discrete FPGAs. This significantly expands our SAM for eFPGA hard IP and discrete devices, including our SRH FPGA, chiplets, and other storefront opportunities.

We initiated our digital proof-of-concept chiplet program earlier this year as a strategy to accelerate our storefront chiplet initiative. Internally, we refer to this as POC.

With the support of our large strategic partners, we have leveraged our existing eFPGA Hard IP and readily available third-party IP to move forward rapidly and with minimal investment.

In line with the forecast I shared in our last conference call, we completed the initial phase of the digital FPGA chiplet POC, where the eFPGA IP is connected to UCIe IP and the necessary interface logic for the IPs to communicate.

This digital simulation of the POC is available now and can be further developed to meet different customer requirements. Together with our ecosystem partners, we are engaging with prospective customers in the defense, aerospace, industrial, and commercial markets.

We plan to move forward with the next phases of the FPGA chiplet POC once external funding is committed. This phase will include incorporating additional IP, such as programmable GPIOs, AXi Bus, DSPs, data converters, and interfaces such as PCI Express, to meet specific customer requirements.

We are optimistic that our POC initiative will lead to storefront revenue in 2026. On October 2, we announced a new $1 million eFPGA hard IP contract for a high-performance data center ASIC that will be fabricated on TSMC's 12-nanometer process.

In this ASIC, our eFPGA Hard IP will be the primary IP in the design. This contract is a great illustration of our success in several of the points I mentioned earlier.

The need for larger blocks of eFPGA, the increasing value contribution of eFPGA and customer designs, winning contracts for designs targeting advanced fabrication processes, and our growing success in commercial market sectors.

We will soon announce the expansion of our involvement with a DIB that specializes in cybersecurity for strategic and tactical weapon systems. This DIB designs secure system-on-chip processors that leverage the enhanced security that only eFPGA can provide.

Running these processes and hardware is inherently more secure than software solutions. With eFPGA at the heart of the designs, the hardware can be altered to respond to new threats and updated algorithms.

We are proud to have been chosen as a trusted supplier of eFPGA hard IP for these designs. Last April, we announced an eFPGA Hard IP contract with a new defense industrial-based customer valued at $1.1 million that will be fabricated on the GF 12LP process.

This application utilizes a large block of our eFPGA Hard IP for critical functions, which is a trend we are seeing, particularly in designs targeting advanced fabrication nodes.

With the cooperation of this DIB and its end customer, we are leveraging the large eFPGA core into a new 7-figure contract we expect to announce in the coming weeks.

In the scope of this new contract, we will be provided with test chips that we will incorporate into an evaluation kit. The evaluation kit will be compatible with common third-party development environments used by both DIBs and commercial customers.

This enables these customers to accelerate system-level evaluations and designs that can use either a storefront version of the 12LP test chip or our eFPGA Hard IP in an ASIC. We anticipate having evaluation kits available in late 2026.

With that, I will turn the call over to Elias for his presentation of financial data.

Thank you, Brian, and good afternoon, everyone. Total third-quarter revenue was $2 million and aligned with the midpoint of our guidance.

Total revenue was down 52.5% from Q3 2024 and down 45% compared to Q2 2025. Rounded to the nearest $100,000, new product revenue in Q3 was $1 million, and mature product revenue was $1.1 million.

New product revenue was down 73.1% from Q3 2024 and down 67.3% compared to Q2 2025. Mature product revenue was up from $0.7 million in the third quarter of 2024 and up from $0.8 million in the second quarter of 2025.

Non-GAAP gross margin in Q3 was a negative 11.9%. This compares with the non-GAAP gross margin of 65.3% in Q3 2024 and 31% in Q2 2025.

The primary reasons for the lower Q3 gross profit margin are unfavorable absorption of fixed costs due to lower revenue and the fact that $300,000 of R&D costs were allocated to COGS.

Non-GAAP operating expenses in Q3 were approximately $2.9 million. This was approximately $300,000 below the midpoint of our outlook due to the COGS allocation I just mentioned.

This compares with non-GAAP operating expenses of $3.3 million in the third quarter of 2024 and $2.5 million in the second quarter of 2025.

Non-GAAP net loss was $3.2 million or $0.19 per diluted share. This compares to non-GAAP net loss of $0.9 million or $0.06 per diluted share in Q3 2024 and a non-GAAP net loss of $1.5 million or $0.09 per diluted share in the second quarter of fiscal 2025.

The difference between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses, impairment charges, and restructuring costs.

Stock-based compensation for Q3 was $0.8 million. Stock-based compensation was $1.2 million in Q3 2024 and $0.8 million in Q2 2025. Impairment charges were $0.3 million in Q2 2025.

For the third quarter, 3 customers accounted for 10% or more of total revenue. At the close of Q3, total cash was $17.3 million, inclusive of utilization of $15 million from our $20 million credit facility.

This compares with $19.2 million, inclusive of usage of $15 million from our $20 million credit facility at the close of Q2 2025. Net of approximately $200,000 raised with our ATM in July, cash usage during Q3 was approximately $1.9 million.

This was primarily driven by tape-outs and wafer costs associated with our internally financed SRH FPGA test chip. In addition to these one-time costs, there were also expenditures related to revenue contracts and repayments for finance tooling and equipment.

Now moving to our guidance and outlook for our fiscal fourth quarter, which will end on December 28, 2025. Based on backlog and customer forecast, we are targeting a total revenue of $6 million for Q4.

Many of the contracts that support this outlook are already on the books or have been forecasted by customers to be awarded during the coming weeks.

However, the customer for a contract valued at nearly $3 million for commercial application has forecasted the award for late in the quarter. If this contract is awarded on or very near the date forecasted, we will be able to recognize a large portion of that revenue in Q4.

And with that, we realize our $6 million objective. We have a very high level of confidence in winning this contract, but note that it could push into Q1 2026, and that would result in Q4 revenue of $3.5 million.

Due to this, our guidance range for total Q4 revenue is $3.5 million to $6 million. At $3.5 million, we expect total revenue to be comprised of $2.5 million in new product revenue and $1 million in mature product revenue.

At $6 million, we expect $5 million in new product revenue. Based on the anticipated Q4 revenue mix, non-GAAP gross margin for the fourth quarter is expected to be approximately 45% at $3.5 million of revenue and 68% at $6 million of revenue.

At the low end of the range, the primary reason for the lower gross profit margin is attributed to less favorable absorption of fixed costs. Taking the range of our Q4 outlook into consideration, our full-year 2025 non-GAAP gross profit margin is expected to be 38%, plus or minus 5%.

Our Q4 non-GAAP operating expenses are expected to be approximately $3 million, plus or minus 5%. With this, we are modeling that full-year 2025 non-GAAP OpEx will be approximately $11.3 million.

Please note that, given the nature of our industry, we may occasionally need to classify certain expenses to COGS versus OpEx or capitalize certain costs.

These classifications are related to labor and tooling for our IP contracts with customers. This may cause variability in our quarterly gross margins and operating results that will usually balance out on the operating line.

After interest and other income, at the low end of the revenue range, we forecast a Q4 non-GAAP net loss of approximately $1.9 million or $0.11 per share.

At the high end of our revenue range, we are projecting a non-GAAP net profit of approximately $600,000 or $0.04 per share.

The main difference between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses. In Q4, we expect this compensation will be approximately $800,000. This is the same as Q3 2025 and down slightly from Q4 2024.

As a reminder, there will be movement in our stock-based compensation during the year, and it may vary each quarter based on the timing of grants.

Even at the low end of our revenue guidance range, we anticipate positive cash flow in Q4. However, the timing of payments from our U.S. government contract could negatively impact this outlook.

Given the fact that we raised approximately $2 million using our existing ATM in October, we are well prepared for any delayed payments associated with the U.S. government contract.

Thank you. With that, let me now turn the call over to Brian for his closing remarks.

Thank you, Elias. We have logged considerable progress during the last few months, and we are leveraging that progress to produce tangible results.

Earlier, I talked about those results. And now I would like to take the next few minutes to help you understand the industry trends that are driving these results.

With that understanding, I think you will appreciate what is driving the increased interest in FPGA technology and why more companies are incorporating larger blocks of eFPGA at the core of new ASIC designs.

The overarching trend in both commercial and design is smart systems. Smart systems rely on algorithms for their intelligence. Algorithms can be processed much faster and with much lower power consumption in hardware than in software.

Hardware processing is also inherently more secure against cyber threats than software. The challenge here is that algorithms must be updated over the life cycle of the product. This means hardware must be programmable so it can adapt to changing algorithms.

This has led to the need for larger blocks of eFPGA at the heart of ASIC designs versus past use cases where small blocks of eFPGA were more commonly used as programmable connectivity bridges. This means both the need and the value proposition for eFPGA are increasing.

Sophisticated smart system designs typically target advanced fabrication nodes. This means higher fixed costs and longer design cycles for ASICs. To favorably offset these higher fixed costs, ASIC designs must deliver longer life cycles than in the past.

Designs that employ eFPGA can adapt to changing algorithms, evolving functional requirements, and external changes that are not evident during the design cycle.

This flexibility lengthens the life cycle of ASIC designs and provides program managers with the confidence to move ASICs to production more quickly and with lower risk. This shortens design cycles and lowers development costs.

Last but certainly not least, there are many programs in development today that must be compliant with rigorous environmental requirements ranging from radiation-tolerant to strategic rad-hard.

Our internally funded development of an SRH FPGA test chip is designed to address the full range of these requirements and accelerate our ability to pursue design wins.

By using the same onshore 12LP fabrication process that DIBs have used for SRH ASICs, we are optimizing our chances of winning discrete FPGA designs we can storefront and contracts for eFPGA Hard IP that customers can incorporate in ASIC designs.

Further enhancing our position is the fact that customers can execute designs with our Aurora user tools for both. The fact that this investment by QuickLogic has been received very well by strategic DIBs is underscored by the commitment we have for SRH dev kit orders that we anticipate receiving by the end of this month.

Before I turn the call over for Q&A, I want to take a moment to recognize Veterans Day and express my heartfelt gratitude to all those who have served our country.

This day has personal meaning for me as several members of my family have served, and I have deep respect for the sacrifices made by veterans and their families.

It's something we honor at QuickLogic, especially as we develop technologies that contribute to our nation's defense and security.

Operator, I would now like to open the call for questions.

[Operator Instructions]

Our first question comes from Quinn Bolton with Needham.

It's Neil Young on for Quinn Bolton. So the question I wanted to ask, Neil, like I said, on for Quinn. Sorry about that. So what impact is the government shutdown having on your business?

Based on the prepared remarks, it sounds like you've seen some delays in projects. Have you seen any cancellations? And then, given the ongoing shutdown, although it is allegedly supposed to end soon here, what gives you confidence in a rebound of the USG strategic radiation Arden FPGA program in 4Q? And then I have a follow-up.

Yes. I think, firstly, let's zoom out. Programmable logic has been a big part of the defense industrial base for decades, and that's not changing. It's pervasive across like 75% of defense systems.

And as I mentioned earlier, a very large percentage of the total semiconductor spend by the DoD. So that demand is not going away. The question is, as you get down to the nuts and bolts of these programs, is the funding going to be there based on the budgets and whatnot?

So I think that from the programs that we have today on contract, we're not seeing any delays with those. Elias did mention in his conversation about the cash usage for the quarter, or I should say, net cash gain in the quarter.

We did use the ATM in October as an anticipation in case there was something like this that happened as far as funding goes. So if there's a delay in funding, then we have no issue with that. If there's no delay, then we'll have a good positive cash flow for the quarter.

Aside from that, if you look at other contracts coming down the pipe, I mean, you could find this all publicly that a lot of the new RFIs or RFSs or RFPs that were coming out from the government for various development programs, some of those were actually paused.

And I think that's largely because some of those workers who were driving that were put on furlough. Again, I don't anticipate those going away permanently. It's more once the government is funded and people get back from furlough; these are going to be full steam ahead.

So you might see a delay in some of those new programs, but not the ones that we're fully executing on today. I just don't see that change because this is not an experimental technology. There are actual programs of record that need this today, and moving forward on that. Does that answer your first question?

Yes. And then the second question I want to ask. So it sounds like storefront revenue in 2026 is supposed to have a meaningful step-up.

If possible, I was wondering if you could maybe size the range of storefront revenue you think is possible? And then if not, maybe you could give us some idea of what could drive upside to your internal expectations, or on the other side, perhaps drive downside to those expectations.

Sure. I'll start with the what, and then I'll answer with the why. So on the what side, I mean, I would say significant for us is going to be the 10% or thereabouts of total revenue.

And without giving the exact number because we haven't put numbers out for 2026 yet, we think that the storefront revenue associated with these developments that we've been talking about is going to be meaningful, meaning it will be in that 10% range.

And yes, I do think next year's revenue will be notably higher than this year's total revenue. As you get into Why do I feel like that? I think if you go back to my opening remarks about the strategic router initiative, I cannot tell you how many meetings I've had in the last quarter since the last conference call, face-to-face with these DIBs, who see what we're doing.

They like the fact that we've done this tape-out that we talked about. And even as of today, lots of calls and e-mails are asking for when they can get their hands on this. And so when you start to see people pulling for the technology, and you know the projects that are under development, public projects.

The strategic defense system is going through a major modernization. That's all public knowledge. And then if you throw into that, this notion of hypersonics and golden dome, a lot of these programs are going to need some level from strategic radar down to radiation tolerant.

And the part that we've got in the fab now is designed to address those needs. So as we get it out, we start moving to these orders for dev kits, we start getting those out, hopefully, by the end of Q1, I think we're going to be in a real prime spot to monetize that and start turning talk that I've had for 2.5 years into actual revenue and bottom line contribution.

But it's not just one entity here. We're talking about all the major DIBs that we've been talking to. I think there's good demand for that. So that's why we think it's going to be meaningful for next year. Does that answer your question?

Our next question comes from Richard Shannon with Craig-Hallum.

The quality of the audio here is pretty poor for my answer. Hopefully, you can hear me. Apologize if you can't hear.

Okay. Let's go. I guess at least one of us can. A lot of detail on the call here, and some really interesting stuff is going on here. Let me ask a big picture, high-level question here with your new initiative on the GF12LP process or initiative here.

I guess, how do we think about the opportunity for FPGAs versus ASICs that would include your hard IP in here? And are the dynamics here for timing for each of these markedly different from the other?

Well, I'd start by saying for 12, that is a very commonly used process by the defense industrial base. I think the heritage of that is that that was the most advanced process that GlobalFoundries and GlobalFoundries is U.S.-owned and operated.

And so if you wanted to have something that was manufactured onshore by a U.S. company, that was the most advanced you can get. Global has since come out with 12LPus, which is a more advanced version of 12LP.

But if you think about what's involved in doing an ASIC or an SoC, you need lots of IP available, and you need lots of test data characterization on all that IP in order to feel comfortable moving forward with that on your ASIC.

And in terms of the defense community, it's a very risk-averse community, as they should be, as they're designing the system. So there's a wealth of IP on 12LP that there is, it's today, it's known, it's understood, characterization data. And the government, again, this is all publicly fungible.

The government has been helping people do ASICs on 12LP. A lot of IP is available. There are government-funded multi-project wafers and all those things to encourage development on that node.

So from that standpoint, I think you're going to see 12LP a lot. You've seen it in the past, you're going to see it in the future. So then the question for us is, okay, we have our IP on 12LP. Now we can build devices from that or we could build or we could license that for people doing their own ASICs.

And I think we've already talked about IP licenses that we have on ASICs, and you've heard timing on that. So people will start to be taping up those and going to production, hopefully, in the next few years.

So there's a near-term license opportunity. There's a back-end royalty opportunity for us on that. And we definitely plan to monetize that to several million dollars a year.

On the device side, that gets interesting because we've obviously taken our commercial 12LP and we've done rad-hard implementation of that.

So the goal behind that is to do this strategic rad-hard FPGA and having to take that out, if you fast forward to when we could do that actual product die for production on that, once that's out, that's going to be a significant step function increase in the revenue potential for us personally because devices of that nature are always going to have a much higher ASP than what a royalty contribution would be.

So I think 12LP is critically important for us. And it's a land and expand strategy on that now. We want to license it to as many people as we can. We want to have this strategic FPGA capture for revenue.

And that's, I think, the basis of what could be hundreds of millions of dollars in revenue. I don't know if I answered your question. It's an entirety. If I didn't, just tell me.

You did for the most part. I'm just trying to circle around this a bit here from a very high level. I'm going to ask another pretty high-level question here, Brian, which is comparing the opportunity you've now undergone with GFS 12LP.

How do you compare the opportunity to what you've been doing with rad-hard with the other foundries you've announced with? I guess, from a total perspective overall, I'll let you pick a time frame. But how do you see the relative size of each of these opportunities.

By the other founders, you're referring to SkyWater and Honeywell or somebody else?

Those are the ones, yes.

Okay. So I think without getting into programmatic details, I think that the 12LP opportunity for us is a larger opportunity because it has the strategic router FPGA. It also has IP licensing as an option.

And one of the nice things, and you know this, is that as you get smaller process technology, you get denser transistors, you get more capability, you can stuff in a die, and there's going to be higher value to that.

And we enumerated that as far as like where we're taking our eFPGA architecture, but the same is true at 12-nanometer and 12LP. The more transistors and functionality we can stick on that die, the higher the value of the part is going to be.

And I think, again, the interesting part about 12LP here is that we can get a lot of capability running on our FPGA, 12LP, and maybe somebody doesn't even need to do an ASIC now for 12LP. That's huge.

If we can start helping people address the needs of a mission without having to go off and do a custom ASIC, you're talking about saving a customer or the government literally tens of millions of dollars in years of development cost and time.

And that's the real benefit, I think, to getting our FPGA on 12-nanometer, given that it's strategic right heart and so capable of the node. Now, as you talk about those other foundries, those are older process geometries that they've talked about.

And so there's going to be a difference in what you can do on the die. There's a difference in what you can do capability-wise, not bad, just different.

But I think the bigger bucket of revenue for us is going to be what we're going to be able to do at 12-nanometer on these for the time being. And I don't want to get into more on that, just because that's a little too much programmatic information if I go further.

Yes. I get that. Just a high level here is very helpful to think about, Brian. You mentioned expecting orders for your new dev kits here, I think, by the end of this month, and delivering those sometime next year. Can you give us a sense of how many dev kits and how many customers you expect to ship that to?

And then what's the design cycle once customers get that in hand in terms of their next steps?

So I'm not going to give numbers, probably not surprised to hear that. But it's going to be enough that it will be a significant revenue number, so not just a rounding number on the income statement.

Elias talked about the money that we spent in Q3 on that. We've intentionally bought enough die that we can provide enough for these customers who want to test these things out, both in terms of dev kit and on just raw devices themselves on their own boards.

Now, the way this works from an evaluation perspective, again, this is a very cautious and risk-averse community that we're talking about. They're going to want to do their own testing on these things, and that generally takes a couple of quarters to go off and do all of your exercising of your design and the different environmental tests that need to need to be done on those devices.

You've probably read the TRL levels, technology readiness level. We want to get customers as quickly as possible, and TRL5 is where they can actually say that they've taken the part and they run it through the rigorous testing that's representative of the environment that they're going to operate in.

And so we hope to be able to support our customers to get through that at some point through the middle of next year, and then at that point, start intercepting actual programs of record with us and moving into pretty late stages of the design, hopefully, with them.

And again, that's why time is so critical. That's why we took the leap of faith to do their own design and fund our own tape-out, knowing that MPWs don't come along very often, and we wanted to make sure that we're on one that still gave us enough time to have the part come out, verify it and get into the hands of the chip so that they can start playing with it in their own labs and not just trust our own data.

Last question, I'll jump out of the line. A lot of irons in the fire that you have going on here, which is great to see here. And then QuickLogic, obviously, is a fairly small company here. It seems like it might need a bit more support for a broad range of customers coming your way here very soon.

How do we think about the spend levels we need to see next year, whether it comes through OpEx or stuff that gets allocated to COGS here? How do we think about where this could go if things go really well and you get a lot of attention, a lot of activity with these dev kits are sending out?

So I'll start and answer, and Elias can chime in on those. So from the engineering perspective and the go-to-market team perspective, we obviously have identified certain critical hires.

Some of them you can find on our website today, and these are all about getting the right resources to get the devices out into the hands of the as soon as possible. And you can find that on our website, engineering, field application engineering, and so on.

As we move from the test chip to the actual product chip, there will be more expenses. There will be other things that need to be paid for. And I think that we have a good line of sight on what those are going to be. And it's not going to be outrageous for next year.

I think it's going to be very mindful of where we are financially as a company and tied in with getting these customers on board with Test chips so that any investments we do make is coming from the perspective of knowing what our customer wants, knowing the problem that our solution solves and in some cases, even perhaps getting funding from customers to co-invest in these things so that they have skin in the game and it offsets the upfront cost for QuickLogic to get it to market.

Yes, correct. And in fact, Richard, if I may add, like, for example, we have 3 new hires we're looking for, all engineers. And as such, OpEx is definitely headcount moderating.

So I don't anticipate even with all the additions that Brian is describing, we'll be looking at probably $3.5 million of OpEx per quarter, probably next year, but starting in Q2 or so. I think for now, we're okay with about under $3.

[Operator Instructions]

Our next question comes from Rick Neaton with Rivershore Investment Research.

I'd like to understand your Q4 guidance. Are you proposing an either/or situation where we're either going to have $3.5 million plus or minus or $6 million, plus or minus? Is that what you're saying?

Yes, because there's an issue with timing. So if the order comes in, for example, to complete it to $6 million, it would come in late in the quarter, and we may be able to recognize certain portions of that revenue.

But if it comes in and we're not able to deliver in that quarter, let's just say it comes in on the day of our close or the day after, it's definitely Q1 at that point.

So it's almost like a timing issue, Rick. And that's why we went to great pains to identify the difference between a $3.5 million revenue and a $6 million revenue, and really, it's one order.

And as such, it's all about timing. So it's very difficult to answer a question now to someone saying, Okay, would you be able to recognize 100% of it? And the answer is clearly no, if it comes in, in Q4. So that is why Brian and I agreed, if that's the case, and we anticipate that order coming in, at least in Q4, let's just hope it does, we at least have the possibility of beating the high end of the range.

What do you forecast as your share count for 2025?

Well, 17,090,252 shares. That's all outstanding right now.

Okay. Final question. So that's your ending share count would be 17. 3 months ago, you described your expected revenue decline for 2025 with the adjective modest. And now your Q4 guidance suggests a 20% to 30% decline in annual revenue from 2024.

What changed since August to cause what I would describe as a significant double-digit percentage-wise revenue decline?

Rick, that's the challenge with having large IP contract values when we're talking $3 million type ASPs for these.

So I think in the call, we mentioned one clearly is in 2026. So that goes from this year into next year. And then some other smaller ones that contribute to that.

But again, when you have $3 million IP contracts, if they don't happen in the year, the fiscal year, there's going to be a big change in percentage-wise from the revenue levels that we're at today.

Once that becomes more of the norm and we get more of these higher-value contracts like we're talking about now, that starts to smooth out some of that lumpiness. But when we're at the stage where we are now, it's almost unavoidable if something moves out that's going to materially impact the percentage of that.

This now concludes our question-and-answer session. I would like to turn the floor back over to Brian Faith for closing comments.

Yes. I want to thank everybody for joining us today. Hopefully, we'll connect with some of you at one of our upcoming events, including the Craig-Hallum Alpha Select 1-on-1 Conference in New York on November 18, the Semiconductor-focused Annual New York Summit also in New York on December 16, or the Annual Needham Growth Conference in early January 2026. Thank you, and have a good day.

Ladies and gentlemen, thank you for your participation. This does conclude today's teleconference. Please disconnect your lines, and have a wonderful day.

Ladies and gentlemen, good afternoon. At this time, I would like to welcome everyone to QuickLogic Corporation's Second Quarter Fiscal 2025 Earnings Results Conference Call. As a reminder, today's call is being recorded for replay purposes through August 19, 2025.

I would now like to turn the conference over to Ms. Alison Ziegler of Darrow Associates. Ms. Ziegler, please go ahead.

Thank you, operator, and thanks to all of you for joining us.

Our speakers today are Brian Faith, President and Chief Executive Officer; and Elias Nader, Senior Vice President and Chief Financial Officer.

As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including, but not limited to, statements regarding our future profitability and cash flows, expectations regarding our future business and statements regarding the timing, milestones and payments related to our government contracts and statements regarding our ability to successfully exit SensiML.

Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low-power competitive pricing and short time to market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters and other business interruptions that could disrupt supply or delivery of or demand for the company's products and changes in tax rates and exposure to additional tax liabilities.

For more detailed discussions on the risks, uncertainties and assumptions that could result in these differences, please refer to the risk factors discussed in QuickLogic's most recently filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information, which speak as of the respective dates of any new information or future events.

In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR web page that provides current and historical non-GAAP data.

Please note, QuickLogic uses its website, the company blog, corporate Twitter account, Facebook page and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR web page shortly after the conclusion of today's earnings call.

I'd now like to turn the call over to Brian. Go ahead, Brian.

Thank you, Alison, and good afternoon.

Since our last conference call, we have focused considerable engineering resources towards 2 strategic initiatives that we will discuss today. We strongly believe these initiatives will accelerate storefront design wins for our strategic rad-hard FPGA and expand our served available market to include very high-density eFPGA hard IP designs targeting advanced fabrication nodes and eFPGA designs that require certain advanced capabilities. This allocation of engineering resources has pushed deliverables and associated revenue recognition forward for several contracts. This has decreased our revenue outlook for Q3, but it is expected to fuel a substantial increase in Q4 revenue.

Now let's discuss what drove us to make these decisions and the opportunities we expect them to enable beginning in Q4. It has been well publicized that the DoD has prioritized certain strategic defense systems, including Golden Dome. As a result, U.S.-based defense contractors have accelerated the development of the associated programs. Many of these programs will require radiation tolerant and in some cases, strategic radiation-hardened semiconductor devices that are fabricated in the U.S. Due to this, we took steps to ensure we are ready to support this accelerated development.

After working nights and weekends, our engineering team delivered design files on Sunday to GlobalFoundries to fabricate a strategic rad-hard or SRH FPGA test chip using its 12LP fabrication node. This initiative was financed by QuickLogic and is independent from our contract with the U.S. government. Our decision to invest the money and resources to develop this test chip now is based on our belief that it is critical to helping us secure strategic design wins and accelerate our storefront business model.

We have been discussing this initiative with certain large DIBs for a couple of years who have programs in development today that are good candidates for an SRH FPGA. We have designed the test chip to meet their requirements. To ensure we are ready to leverage this opportunity and our accelerated introduction of Australis 2.0, which I'll discuss in a moment, we raised money in June and early July with our established ATM.

We anticipate ROI from our SRH FPGA test chip initiative beginning in 2026. And if we are successful in winning designs, we believe storefront production contracts could be worth hundreds of millions of dollars in the coming years. When we initiated our work to develop an SRH FPGA test chip, we believe certain DIBs would be ready to evaluate it in early 2026. However, during a conversation within the last week with one of the large DIBs, I was advised they would like access to the test chip as soon as possible and told me the test chip as it is defined, may satisfy their program requirements.

I know from speaking with investors at conferences and by phone that many of you are focused on the phenomenal growth potential of our storefront business model. I couldn't agree more, and I can assure you that I am intensely focused on executing the prerequisites needed to realize this objective. These include completing the first tape-out that we internally funded in nearly a decade.

The SRH FPGA technology we've developed is the foundation of our storefront model and getting a 12LP test chip in the hands of the DIBs that are developing strategic defense systems today is a critical element to our success. The importance of demonstrating our SRH FPGA test chip goes well beyond the storefront designs we believe it will enable us to secure. FPGA is the #1 spend category for semiconductor devices by the defense industrial base and custom ASICs are a close second. Together, we believe these 2 categories make up roughly half of the DIB semiconductor TAM.

We expect many of these new strategic designs will use either discrete FPGA devices that we can storefront or embedded FPGA IP we can license in new ASIC designs. By delivering a discrete SRH FPGA test chip fabricated on the 12LP process, we are demonstrating the broader capability of our eFPGA hard IP for ASIC applications that will need to either be radiation-tolerant or SRH.

We introduced Australis in 2021. It is a proprietary tool that we use internally to quickly generate customer-specific eFPGA hard IP, and it provides us with a substantial competitive advantage. While we have refined Australis through the years to enhance these advantages, the release of version 2.0 will mark its first significant update. Our success in advanced fabrication nodes, which include 12-nanometer nodes at GlobalFoundries and TSMC and Intel 18A have led to customer contracts and engagements for very high-density eFPGA IP cores that will require the advancements we are introducing with Australis 2.0. These include an awarded 12-nanometer contract, a pending 12-nanometer contract and a potential Intel 18A contract for a 1 million-plus lot or lookup table production design.

We are also seeing customer requirements for faster core speeds, improved silicon utilization and certain new features for high reliability applications. Australis 2.0 will support these requirements and more. Due to these factors, we have given Australis 2.0 a very high priority. We are confident that we will deliver our first eFPGA hard IP using Australis 2.0 for an existing revenue-generating contract during Q4. While we are also confident this will contribute to a substantial sequential increase in Q4 revenue, some of the revenue that we've pushed forward may extend into early Q1. Due to this, we are conservatively projecting a modest decrease in full year 2025 revenue relative to 2024.

Australis, including the soon-to-be completed version 2.0 is our proprietary hard IP generation tool that we use internally. Aurora is the development tool we provide to our customers. The 2 tools work hand-in-hand and together optimize the efficiency of the design process, hard IP generation and the resulting PPA of the silicon implementation. PPA is an industry term, meaning power, performance and area. Aurora started out as a development platform with open source synthesis, which was fine for trailing edge fabrication nodes and low-to-medium density designs. However, many of the large customers we are currently engaged with prefer the Synopsys Synplify FPGA design tool, which is particularly beneficial for leading-edge fabrication nodes and high-density designs.

To accommodate this requirement as quickly as possible, we adopted Aurora 2.9 to be compatible with Synplify and branded it Aurora Pro 2.9. We discussed this in our February conference call. Since then, we've worked closely with Synopsys to optimize Synplify for our proprietary architecture and seamlessly integrated it into Aurora Pro. This was covered in a press release issued July 28. The integration of Synplify is tailored to QuickLogic's eFPGA architecture and includes optimizations for embedded carry chains, block RAM and DSP blocks. This significantly reduces critical path delays and accelerates design convergence, resulting in up to a 35% improvement in maximum frequency. This integration also delivers up to a 50% improvement in resource utilization as demonstrated by customer designs achieving over 96% lot utilization.

Now a brief update on our U.S. government SRH FPGA contract. Q3 will mark the low point for revenue recognition this year on our U.S. government SRH FPGA contract. We completed our deliverables on schedule and recognized the associated revenue during Q2. We are now waiting on the completion of key deliverables from a subcontractor. Due to this, revenue recognition from our SRH FPGA contract will be de minimis in Q3, followed by an anticipated rebound in Q4 that is funded by the current tranche.

As we previously announced, we delivered customer-specific eFPGA hard IP for a customer test chip targeting Intel 18A late last April. This test chip is moving through fabrication, and we expect to have our allocation of test chips to be in hand for evaluation towards the end of Q4. We have booked a second test chip contract with this U.S.-based customer valued at $500,000 that is scheduled for delivery in Q3. In addition to this, we have also been awarded a 6-figure feasibility contract for a 1 million-plus lead design that we are scheduled to complete in Q4. We anticipate this will lead to an eFPGA IP contract for a high-density chiplet design during the first half of 2026.

In our May conference call, I stated that a mid-7-figure contract with this customer targeting Intel 18A was delayed due to the timing of government funding. The customer advised us that it was awarded funding for the program, but funding for the production ASIC, which is a subcomponent of the program would not be awarded until Q4. Beyond the base of business we are rapidly building with this customer, we have multiple Intel 18A engagements with other DIBs and with commercial customers that we believe will result in significant contracts beginning in Q4.

Last quarter, I mentioned that we were in early discussions with customers regarding a digital proof-of-concept chiplet strategy that would give them a head start in chiplet development while standards are still in a state of flux. These discussions have expanded to include 2 of our large strategic partners who will actively help us promote the digital proof-of-concept chiplet we have jointly specified directly to potential end customers as a QuickLogic storefront device.

Due to the fact we can leverage our existing library for the eFPGA core in the chiplet and integrate that with readily available third-party IP, the digital proof-of-concept chiplet will be completed before our next conference call and will be a low-cost investment with potentially very high return as a storefront device. It will be designed to target any of the advanced fabrication nodes we've discussed and can be easily modified to fit customer-specific requirements. Please note this digital proof-of-concept chiplet initiative will not utilize engineering resources that we have dedicated to Australis 2.0, our 12LP SRH test chip or revenue-generating hard IP contracts.

Before turning the call over to Elias, I would like to take a moment to acknowledge the passing of Christine Russell, who served as a QuickLogic Board Director and Audit Committee Chair for 2 decades. She was a dear friend and will be missed. Ron Shelton has joined as a new member of our Board of Directors and will assume the role of Audit Committee Chair. Ron has served as Chief Financial Officer for both public and private semiconductor companies for more than 25 years and is very well respected across Silicon Valley. Ron is also very well connected with investment bankers and analysts, some of whom already cover QuickLogic. We look forward to his strategic insights and guidance contributing to the company's continued growth and success.

With this, I will turn the call over to Elias for financial results and outlook.

Thank you, Brian, and good afternoon, everyone.

Total second quarter revenue was $3.7 million. Total revenue was down 10.7% from Q2 2024 and down 15% compared to Q1 2025. Revenue was below the midpoint of guidance due to lower discrete FPGA revenue and slightly lower revenue recognition from existing IP customers than we had forecasted. New product revenue in Q2 was $2.9 million, down 4.5% from Q2 2024 and down 22.3% compared to Q1 2025. Mature product revenue was $0.8 million, down from $1.1 million in the second quarter of 2024 and up from $0.6 million in the first quarter of 2025.

Non-GAAP gross margin in Q2 was 31%. This compared with non-GAAP gross margin of 54.4% in Q2 2024 and 47.1% in Q1 2025. The primary reason this was below our outlook include the fact approximately $350,000 of R&D costs that we projected would be allocated to OpEx were instead allocated to COGS. In addition, we took an inventory reserve of a little over $100,000. Beyond that, it is attributable to less favorable absorption of fixed costs due to lower-than-anticipated revenue, product mix and certain investments that have been detailed by Brian.

Non-GAAP operating expenses in Q2 were approximately $2.5 million. This was approximately $350,000 below the low end of our outlook due to the COGS allocation I just mentioned. This compares with non-GAAP operating expenses of $2.9 million in the second quarter of 2024 and $3.1 million in the first quarter of 2025.

Non-GAAP net loss was $1.5 million or $0.09 per share. This compares to a non-GAAP net loss of $0.7 million or $0.05 per share in Q2 2024 and a non-GAAP net loss of $1.1 million or $0.07 per share in the first quarter of fiscal 2025. The difference between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses, impairment charges and restructuring costs. Stock-based compensation for Q2 was $0.8 million. Impairment charges for Q2 were $0.3 million and restructuring costs for Q2 were $21,000. Stock-based compensation was $0.9 million in Q2 2024 and $0.9 million in Q1 2025. Restructuring costs were $0.1 million in Q1 2025.

For the second quarter, 3 customers and 1 distributor accounted for 10% or more of total revenue. At the close of Q2, total cash was $19.2 million, inclusive of utilization of $15 million from our $20 million credit facility. This compares with $17.5 million, inclusive of usage of $15 million from our $20 million credit facility at the close of Q1 2025. Net of the approximately $2.9 million raised in ATM sales during the quarter to support the strategic objectives Brian has outlined, our cash usage in Q2 was approximately $1.3 million.

Now moving to our guidance and outlook for our fiscal third quarter, which will end on September 28, 2025. Revenue guidance for Q3 2025 is approximately $2 million, plus or minus 10%. Third quarter revenue is expected to be comprised of approximately $1.1 million in new products and $0.9 million in mature products. As Brian stated in his remarks, our decision to focus engineering resources on the tape-out of our SRH FPGA test chip and the accelerated introduction of Australis 2.0 pushed out deliverables and the associated revenue recognition for several contracts. This decreased our revenue outlook for Q3, but it is expected to fuel a substantial increase in Q4 revenue. Based on the anticipated Q3 revenue mix, non-GAAP gross margin for the third quarter is expected to be approximately 5%. The lower gross margin is attributable to the unfavorable absorption of fixed costs due to lower anticipated revenue.

With the significant revenue rebound we anticipate beginning in Q4, we are modeling full year 2025 revenue will be modestly lower than 2024 and full year 2025 non-GAAP gross profit margin in the low-to-mid 50% range. Our Q3 non-GAAP operating expenses are expected to be approximately $3.2 million, plus or minus 5%. We are modeling our non-GAAP OpEx to be approximately $12 million for fiscal year 2025.

Please note that given the nature of our industry, we may occasionally need to classify certain expenses to COGS versus OpEx or capitalize certain costs. The classifications are related to labor and tooling for our IP contracts with customers. This may cause variability in our quarterly gross margins and operating results that we usually balance out on the operating line.

After interest and other income, we forecast that our Q3 non-GAAP net loss will be approximately $3.2 million to $3.4 million or $0.20 to $0.22 per share. The main driver between our GAAP and non-GAAP results is related to noncash stock-based compensation expenses. In Q3, we expect this compensation will be approximately $0.9 million. This is the same as Q2 2025 and is down $300,000 from Q3 2024. As a reminder, there will be movement in our stock-based compensation during the year, and it may vary each quarter based on the timing of grants. We're anticipating Q3 usage will be similar to Q2 '25 and rebound to solidly positive cash flow and non-GAAP profitability in Q4.

Thank you all. With that, let me now turn the call over to Brian for his closing remarks.

Thank you, Elias.

The decisions we made during the second half of Q2 to prioritize the tape-out of our SRH FPGA test chip on GlobalFoundries 12LP process and maintain the accelerated release schedule for Australis 2.0 were not made lightly. While these decisions have dramatically reduced our revenue outlook for 1 quarter, the upside potential of the investments is exponential. With these investments, we have an opportunity to accelerate our storefront business model and significantly expand our served available market to address applications that require high-density FPGAs. This is a very large market that is currently dominated by discrete FPGAs from our largest competitors. Expanding our capability to integrate these traditionally discrete FPGA designs into ASICs using Australis 2.0 is a huge opportunity for QuickLogic that we will be ready to execute in Q4.

I realize we have provided a considerable amount of new information today. Due to this, we've done our best to keep our presentation concise today to allow more time for your questions.

With that, we will now open the call for Q&A. Alicia, back to you.

[Operator Instructions] Our first question comes from the line of Rick Neaton with Rivershore Investment Research.

In asking digging into your strategic decision to advance the test chip in Australis over more certain business that could possibly have accrued in Q3. It sounds like from your descriptions of the density of some of what you're targeting that you're actually targeting the most widely known competitors in the FPGA market, namely Intel's Altera, while it's still at Intel and AMD Xilinx in the U.S. How quickly can this particular defense business ramp in the storefront business over the coming quarters? Can you give us some color on that?

Yes, I can. And I think one of the points we're trying to convey in the prepared remarks is just how fast this is moving with the engagement with the defense industrial base and what accelerated, in particular, the tape-out that we funded on the strategic rad-hard FPGA. So I think the short answer is that we could start seeing some test chip revenue very early 2026, and we're anticipating having some of these devices on boards for customer engagement. And that's based on our ability to supply those.

If we think about the demand side, conversations I've been having over the last couple of weeks have really emboldened us to go and accelerate this tape-out because I think we can all see from the news that there is a tremendous push not only to strengthen the systems that give us national security, but to do those in a way that they're manufactured and fabricated in onshore foundries.

And if we look back at the last 2 years of the developments that we've been doing, more often than not, our eFPGA IP core developments have been in U.S. foundries. With GlobalFoundries on 12LP and 22FDX and with Intel on 18A. And I think knowing that, that demand is there, I think we've said multiple times now the DoD spends north of looks like $5 billion a year on semiconductors. And I think roughly half of that is a mix of FPGA and ASIC. So the sooner we can get an FPGA test chip taped out and manufactured in the hands of people, we can start engaging on storefront revenue on that. The sooner we can get IPs done, we can start getting inserted into ASICs, that's the #2 category. And of course, we can start monetizing that when we license.

But again, back to your direct storefront question, I think the fact that we're taping this out now gives us the ability to start monetizing from test chips perspective in 2026. And who knows, that could lead to even end of year or early 2027 for more volume-oriented device sales on that technology. So I think it's absolutely the right decision that we accelerated that because if you're thinking about, do I do $1 million or $2 million more revenue this quarter and then forgo the chance to get into multi-hundred million dollar markets in the defense area with all this going on and these new systems being deployed, that's the wrong decision for investors.

The right decision is to make sure that we have the chips on the table for when these companies are making these decisions on microelectronic components that go into the national defense types of systems that are going to be coming online in the next few years. And that's the bet that we've made. And I think that's absolutely the right bet to do that.

How closely are you engaged with these prospective customers that you feel certain enough to make this change in course and actually do a tape-out because over the last few years, you've talked about the benefits of just licensing IP, getting royalties and then perhaps some limited storefront activity. So how engaged are you with these people that you made this change of course?

So I'd say, firstly, that we've been on the path of doing developments for storefront for the last several years. IP has obviously been a big part of the business model as well. But we had our eye that we wanted to have more products or capability on the storefront side because we know that those drive the top line considerably higher and faster than IP licenses. So having this blended business model was the right model for the company.

As you know, since our inception 35 years ago, whatever it is now, defense has always been a big market for QuickLogic. And I've always been very connected to that industry as well, dating back to when I first started here. I'd say in the last few years, the activity has really picked up in that area as far as customer engagement goes. Some of it just typical discussions you have with existing customers. Some of it's been accelerated because of the exposure that QuickLogic is getting from doing work for the government directly now and also some of the speaking engagements we've been afforded at these big foundry events like the one with Intel Direct Connect a few months ago. And I think those discussions have led to much deeper discussions around program needs and architecture needs.

And again, just in the recent time, you can see that there is a concerted push by our government to have onshore manufactured alternatives to what has historically been an overseas manufactured technology, semiconductors and more specifically FPGAs. I can tell you that when it comes to deciding to self-fund a tape-out, and we haven't self-funded a tape-out in nearly a decade, no exaggeration. I take that very seriously.

And I am talking directly to these customers to know that there is actually an opportunity to serve there that we solve a problem, a fundamental problem that they have budget to do, and they want to use these parts. And so that's what gave me the confidence and the team the confidence to do that. And I think that also gave the team a lot of motivation, the engineering team in particular, to work nights and weekends to get that tape-out done so that we could intercept the MPW schedule. And kudos to them for doing that because I think they also believe and see the opportunity that's steering right in front of us. Does that answer your question?

So you talked about intercepting the schedule. Are you trying to displace an existing vendor? Or is this something different?

I would say this is something different because if you think about certain programs, certain programs are not able to use offshore manufactured capability. It has to be onshore. And today, there's no production FPGA that's manufactured onshore, not the least of which would be, is it rad-hard? Is it some of these other capabilities that we're talking about. So we're doing this because we want to be a viable alternative to what people historically do, which is go spend a lot of money doing a custom ASIC.

When we have standard products available, that's great because they're available immediately. They don't have to wait for an ASIC design cycle. They don't have to spend a ton of money on NRE to go do an ASIC design from scratch. And if you think about, again, the rate at which things are changing and the government is trying to get the defense industrial base to launch these new systems, their schedules and budgets don't really afford for the huge expense of ASICs every time. And so in that case, we would actually be an architecture alternative to what has classically just been full custom ASIC path.

[Operator Instructions] Our next question comes from the line of Richard Shannon with Craig-Hallum.

Brian, I guess you've made for a very, very interesting call. I had all this prep done, and that's almost all thrown out the door here, some really interesting stuff going on here. Let me ask a couple of quick questions here. And one of them, I think the first one here is following up on Rick's question here. And it really goes to whether there's any -- and you just explained, I think one of your last sentences here about there's no alternatives here, at least existing in the past. So my question to you is, to your knowledge, do you know of anyone else trying to do something similar to this in any way? Could this only be replicated by somebody having embedded FPGA technology? Or can it be done some other way?

I think at the end of the day, if you want custom capability implemented in a microcontroller or a microelectronic device, you can do that as an ASIC or you can do it in an FPGA. And so do I know if anybody is doing an FPGA that's doing what we're doing? I don't think so. There are clearly other FPGAs in the market that are rad-tolerant, less that are rad-hard, none that I know of that are strategic rad-hard and none that I know of that are on GlobalFoundries 12LP. So I think we're pretty well positioned for the capabilities that we have designed into our chip to be very unique and different. And that's what's driving a lot of the interest in the defense industrial base to get their hands on these as soon as we can get them to them.

Okay. So the tenor of these conversations lead you to believe strongly that these are -- as long as you execute our sole source positions.

I would not have authorized this PO if I didn't think there was a very high degree of confidence in winning actual revenue, and I'm talking about the hundreds of millions of dollars of revenue if I didn't truly believe that this was a differentiated and very good investment for us and our stockholders.

Okay. That's very directly stated. Maybe a few other key details on this initiative here. So are all of these opportunities you're going after specifically related to Golden Dome or are they a little bit more broadly across new defense programs? Just want to be clear since that was part of your remarks.

It's much broader than that. We inserted Golden Dome in this just because there's been a lot of press about that recently. And I think there's been a lot of meet-ups, if you will, within the industry around Golden Dome and how that can be accelerated. But this is clearly not limited to Golden Dome.

Okay. And are these all rad-tolerant or red-hard?

Yes. The second you start backing off of rad-hard, rad-tolerant and you're talking about just plain COTS mil-temp, that really opens up a much broader competitive arena. And we're really trying to stay focused in the swim lane where we can be very dominant and very differentiated. And so we are trying to stay focused on rad-tolerant and rad-hard. If an engagement leads in a different direction to mil-temp plastic parts, fine, we'll talk to anybody that wants to buy our devices, but that's not the main thrust behind this.

Okay. And then I'm pretty sure I understand this, but I'm asking a very direct question here just to make sure that I do. So all these devices are inherently higher density that you wouldn't expect to be done on other nodes, specifically the rad-hard you're doing with 2 other foundries you've been working on for a couple of years here. These are not overlapping markets in any way, are they? So this is entirely new. Is that correct?

This is entirely new. This is funded by QuickLogic, completely independent.

Okay. But not overlapping in market in any way.

Not that I am aware of. I mean there's -- where you define like what a super set is and a subset is, that's kind of gray, right?

But I guess my point is it sounds like you're describing this as really high-density stuff on a 12-nanometer node that you wouldn't inherently be able to do on a 90-nanometer node you've been working on with others.

Yes, for sure. Yes, I completely agree.

Okay. Perfect. Maybe last -- 2 last questions. I'll jump out of line here. So it sounds like you're delaying some of the other contracts that we've heard for a number of quarters in past calls here. Is there any negative impacts to any of these contracts by delays as you're focusing on this?

No. In fact, the schedules that we're talking about with customers as a result of the Australis 2.0 capability being prioritized, we're being very forthright with our customers. There's no issue with that. They're working with us on those deliveries. And there's no material impact at all to things that we have in our contract. It's helping shape how we discuss and negotiate contracts for the ones that aren't won yet, but they're very clear in understanding of what Australis 2.0 has.

And like I was saying in the script, some of these customers that we've been engaged with, their desires from our core have actually expanded, and that's what's driven us to actually accelerate Australis 2.0 so that not only can we do the core they need, but we can do it and still have this automation that we need so that we can actually handle multiple cores for multiple customers at the same time.

We could have gone and prioritized, well, let's just do this one customer for revenue in Q3 and let's push out 2.0. And that's the whole thing I was mentioning earlier that we could do that, and that's better for Q3 revenue, but it's actually not better for the company because then we're still in the same situation waiting for 2.0. So this is the bite the bullet, get 2.0 out and done so that we can then use that to fan out to these multiple customers that we're talking about, especially the ones that need the higher density. And we are starting to see more of those now. And that density range clearly needs Australis 2.0. So the sooner we can get that done, the sooner we can start tackling many of these in parallel.

Okay. I think that makes sense. I appreciate all the detail. I got my last question for Elias. So I guess I wanted to maybe try to narrow down a little bit about what you're thinking about for modest decline in revenues and what that can imply for fourth quarter revenues here. Maybe if you can -- if you care to define or help us think about those numbers, that would be a great help.

Well, if you recall what I said is that we're expecting a significant uptick starting in Q4, but we're still going to have a down year, modest down year compared to last year, okay? I don't want to give you a number right now, but we're working on it and would like to pump it a bit down the road because if I gave you a number, I probably would stick my neck out for it, but I would say -- let's just put it this way, I would say it's significant.

Okay. Fair enough. I guess we'll try our best on modeling that, and we look forward to very interesting next few quarters.

Our next question comes from the line of Gus Richard with Northland Capital Markets.

I just had a couple of questions. The first one is, I never heard of a chip company monetizing a test chip. And I believe in the script, you said that you'd be able to get customers to pay for test chips, and it sounded like you were going to sell multiple test chips. I'm just wondering how that works.

Yes, definitely. So test chips are our way of proving out IP functionality before we do the production version of that, right, because it minimizes risk and upfront costs when you do that. But you can definitely sell devices to customers for engineering samples. So test chip and engineering sample can be used interchangeably in this case. But if you're giving a customer access to technology, especially in the markets that we're talking about, and you're doing so in a way that makes it easy for them to use like on an evaluation card, they're very accustomed to paying for those and not getting that for free.

This is unlike 10 years ago when we were doing things in more of the consumer market where the Samsungs of the world expect everything for free up until the first volume purchase order. This is a very different market that we're talking about with aerospace and defense. And so I think they're accustomed to paying for that, and we're expecting that we will be paying for that -- they will be paying for it, excuse me.

So the test, if I've got this right, and you say it's interchangeable with an engineering sample. So this is a fully functional stand-alone FPGA test chip. Is that the way to think about it?

That is the way to think about it. That's right. We've designed it so that our customers can take their IP, their RTL and run it in the FPGA in that test chip.

I see. So it would go along with the demo board or what have you?

Yes, they would get some sort of an evaluation board and then the FPGA user tools, the Aurora tools that we provide for them to run their designs through and create a bitstream.

Got it. And could this test chip be turned into a standard product? Or would there be more engineering required before that would happen?

That's a million-dollar question actually because if these customer evaluations prove out to be fruitful in the sense that they can run their RTL and not many changes are needed, then it's simply production mask call and go, meaning very minor changes. If through that cycle of learning with the customers using the evaluation tools, it shows that we need to -- I'm just using examples here, make it bigger or make it smaller or make it add a different interface to it, then those are all things that are typically very feasible, but they would impact schedule and costs on the development side.

So that's really, I think, why we want to get this test chip out into the hands of the defense industrial base because there's no substitute for them using the part, touching and feeling it and running it through the software so that they know does it work as is or does it need some modification to that. That's the kind of engagement that you can actually have when we get test chips in their hands, which is, again, why we went through this really diligent decision in trying to say, yes, we're going to go accelerate this because we want that feedback. We want to know if this thing can work. And if we can generate revenue next year, starting production revenue by the end of the year, depending on the nature of the changes required.

And is this going to go through on a hot lot? Are you -- is it a multi-project wafer? Sort of what's the mechanism through global?

I'm going to give a little bit more detail. And then if we go deeper, I'll probably say I'm not going to go there. But I'll say most -- more often than not, companies do MPWs because that actually minimizes the cost of the test chip. And that was actually one of the reasons why when we decided to do this, we basically were on the clock to get it done and submitted because there is an MPW that we wanted to intercept. And MPWs are like the Shinkansen in Japan. If you're a minute late, you miss the boat or miss the train. And so we really had to scramble and our engineering team did an amazing job to get everything submitted on time so that we could be on that MPW train. So short answer, MPW, hopefully, that's sufficient for your question.

Yes. And then you would have to run -- if this was a successful chip, you'd have to run more full wafers in order to get samples to customers.

And that's a great problem to have. Global is a fantastic foundry, and I have no doubts that they could handle that if we need it.

Okay. And at the risk of boring everybody, shifting over to the software side, it sounds like you have been using your engineers that work on the design software to help customers design products in your FPGAs and you're taking those customers out of customer support and moving into product development. Is that the way to think about it?

We have different disciplines within engineering. Some people tend to be more customer focused and some are more internally focused. There are some resources that can cross over those domains and do both. And I would say that anybody that could help with getting this tape-out done helped without impacting customer-related programs. So we did do a lot of resource shuffling to make that happen.

Yes. I was referring to the software side, your design software. It sounded like a customer's project was delayed for revenue in Q3 because you're working on your design software.

That's Australis. So Australis is the IP generator. Australis 2.0 needed to go through several feature enhancements to meet the needs of what I was just talking about earlier. And we were basically trying to pull that in and accelerate that. And we're still working on that because we said 2.0 will be available in Q4. And so there are as many resources that we have that are capable of helping with Australis 2.0. We're doing that because we want to get that done and ready in Q4. We don't give Australis to our customers. Our IP engineers use Australis to create IP for customers.

Okay. I understand. But you want that to intersect the test chip in Q4?

No, that's completely different. Australis 2.0 is for our IP licensing. It is not related to the tape-out that we just did.

Our next question comes from the line of Richard Shannon with Craig-Hallum.

Brian, just one follow-on question for me. So you talked about this great deal of interest from various defense programs and specifically the need for onshore manufacturing. You're obviously talking about rad-hard, rad-tolerance on a 12-nanometer node. Does this enthusiasm and acceleration of time frames, are you also seeing this in your strategic rad-hard on the other 2 foundries you've talked about working with for the last couple of years?

We are definitely seeing interest on the DIB on those. I'm not going to be able to go into more detail because that's the government contract, and I'm not allowed. I've asked again for permission to talk about it in more detail, but not been granted that. So I can't really go into more detail. But we are still seeing interest for that as well from an end customer perspective.

There are no further questions at this time. I'd like to pass the call back over to Brian for any closing remarks.

Thank you.

Before we conclude, I wanted to share a few upcoming opportunities to connect. On the investor side, we'll be at the Sixth Annual Needham Virtual Semiconductor & SemiCap 1x1 Conference on August 21 and in New York on September 4 for the TD Securities Technology Growth Cap Summit. We'll also be showcasing QuickLogic at key industry events, starting with GlobalFoundries Technology Summit in Santa Clara at the end of August, then in Munich in October; and finally, embedded world North America in Anaheim this November.

Thank you once again to our shareholders, analysts and the broader investment community for your continued interest and support. We value your confidence in QuickLogic and look forward to updating you on our progress in the quarters ahead. Thank you, and goodbye.

This concludes today's teleconference. You may disconnect your lines at this time. Thank you for your participation.